XR16C872CQ EXAR [Exar Corporation], XR16C872CQ Datasheet - Page 28

• Manufacturer Part Number: XR16C872CQ
• Description: DUAL UART WITH 1284 PARALLEL PORT AND PLUG-AND-PLAY CONTROLLER
• Manufacturer: EXAR [Exar Corporation]

XR16C872
Logic 1 = Force RTS# output to a logic 0.
Automatic RTS may be used for hardware flow control
by enabling EFR bit-6 (See EFR bit-6).
MCR BIT-2:
*OP1# output is not available in the 872.
Logic 0 = Set OP1# output to a logic 1. (normal default
condition)
Logic 1 = Set OP1# output to a logic 0.
MCR BIT-3:
*OP2# output is not available in the 872
Logic 0 = Set OP2# output to a logic 1. (normal default
condition)
Logic 1 = Set OP2# output to a logic 0.
MCR BIT-4:
Logic 0 = Disable loop-back mode. (normal default
condition)
Logic 1 = Enable local loop-back mode (diagnostics).
MCR BIT-5:
Logic 0 = Disable Xon-Any function (normal default
condition)
Logic 1 = Enable Xon-Any function. In this mode any RX
character received will enable Xon.
MCR BIT-6:
Logic 0 = Enable Modem receive and transmit input/
output interface. (normal default condition)
Logic 1 = Enable infrared IrDA receive and transmit
inputs/outputs. While in this mode, the TX/RX output/
Inputs are routed to the infrared encoder/decoder. The
data input and output levels will conform to the IrDA
infrared interface requirement. As such, while in this
mode the infrared TX output will be a logic 0 during idle
data conditions. Care must be taken into consideration
in the design not to over heat the IR LED during power
up initialization state while TX output is still at logic 1.
Example to enable IR encoder and decoder.
Write LCR with 0xBF
Set EFR bit-4 to logic 1
Write LCR with op. value ; set up LCR and point to base register set
Set MCR bit-6 to logic 1
Rev. 1.00
; enable IR mode, TX output pin goes logic 0
; enable non-550 bits in IER, EFR & MCR
; access to EFR “shadow” register
DISCONTINUED
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MCR BIT-7:
Logic 0 = Divide by one. The input clock (crystal or
external) is divided by sixteen and then presented to the
Programmable Baud Rate Generator (BGR) without
further modification, i.e., divide by one. (normal, default
condition)
Logic 1 = Divide by four. The divide by one clock
described in MCR bit-7 equals a logic 0, is further divided
by four (also see Programmable Baud Rate Generator
section).
Line Status Register (LSR)
This register provides the status of data transfers
between the UART and the CPU.
LSR BIT-0:
Logic 0 = No data in receive holding register or FIFO.
(normal default condition)
Logic 1 = Data has been received and is saved in the
receive holding register or FIFO.
LSR BIT-1:
Logic 0 = No overrun error. (normal default condition)
Logic 1 = Overrun error. A data overrun error occurred in
the receive shift register. This happens when additional
data arrives while the FIFO is full. In this case the
previous data in the shift register is overwritten. Note
that under this condition the data byte in the receive shift
register is not transfer into the FIFO, therefore the data
in the FIFO is not corrupted by the error.
LSR BIT-2:
Logic 0 = No parity error (normal default condition)
Logic 1 = Parity error. The receive character does not
have correct parity information and is suspect. In the
FIFO mode, this error is associated with the character
at the top of the FIFO.
LSR BIT-3:
Logic 0 = No framing error (normal default condition).
Logic 1 = Framing error. The receive character did not
have a valid stop bit(s). In the FIFO mode this error is
associated with the character at the top of the FIFO.
LSR BIT-4:
Logic 0 = No break condition (normal default condition)
Logic 1 = The receiver received a break signal (RX was
a logic 0 for one character frame time). In the FIFO
mode, only one break character is loaded into the FIFO.
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