XR88C681CP/28 EXAR [Exar Corporation], XR88C681CP/28 Datasheet - Page 42
XR88C681CP/28
Manufacturer Part Number
XR88C681CP/28
Description
CMOS Dual Channel UART (DUART)
Manufacturer
EXAR [Exar Corporation]
Datasheet
1.XR88C681CP28.pdf
(101 pages)
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Z-80 P can be configured to operate in one of three
different “interrupt modes”. The Z-80 is also a little bit less
complicated to interface to (than some of the P/ Cs
The Z-80 CPU will support Read/Write operations
between memory and I/O. The Z-80 does require some
additional glue logic in order to interface directly to
memory and peripheral devices. For instance, the Z-80
CPU device does not come with the control bus signals:
-
MEMR (Memory Read),
Rev. 2.11
-
MEMW (Memory Write),
-MREQ
-IORQ
-HALT
-NMI
V
-INT
A11
A12
A13
A14
A15
PHI
Figure 17. Pin Out of the Z80 CPU Device
CC
D4
D3
D5
D6
D2
D7
D0
D1
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
-
IOR
Z80 CPU
42
previously mentioned) because its address and data bus
are not multiplexed. Figure 17 presents a schematic of
the pin out of the Z-80 P.
(I/O Port Read),
(Interrupt Acknowledge) pins. Each of these functions
can be derived from the
-
CPU Module, which shows how once can extract the
control bus signals from these CPU control pins.
M1 pins. Figure 18 presents a schematic of the Z-80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
GND
-RFSH
-M1
-RESET
-BUSRQ
-WAIT
-BUSAK
-WR
-RD
-
IOW (I/O Port Write) or
-
RD,
-
WR,
-
IORQ,
-
-
IACK/
MREQ and
-
INTA
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