S9S08LG16J0VLF FREESCALE [Freescale Semiconductor, Inc], S9S08LG16J0VLF Datasheet - Page 31

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S9S08LG16J0VLF

Manufacturer Part Number
S9S08LG16J0VLF
Description
8-bit HCS08 Central Processor Unit (CPU)
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
2.11.3
Table 16
Freescale Semiconductor
No.
10
11
12
1
2
3
4
5
6
7
8
9
and
D
D
D
D
D
D
D
D
D
D
D
D
D
C
Figure 23
SPI Timing
Operating frequency
SPSCK period
Enable lead time
Enable lag time
Clock (SPSCK) high or low time
Data setup time (inputs)
Data hold time (inputs)
Slave access time
Slave MISO disable time
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time
Fall time
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Input
Output
Input
Output
through
Figure 26
Function
MC9S08LG32 Series Data Sheet, Rev. 7
describe the timing requirements for the SPI system.
Table 16. SPI Timing
t
Symbol
WSPSCK
t
SPSCK
t
t
Lead
t
t
t
t
t
f
Lag
t
t
HO
t
SU
RO
FO
t
dis
t
op
HI
RI
FI
a
v
f
t
t
Bus
cyc
cyc
Min
1/2
1/2
15
15
25
/2048
0
2
4
1
1
0
0
0
– 30
– 30
1024 t
t
t
Electrical Characteristics
cyc
cyc
f
f
2048
Max
Bus
Bus
25
25
25
25
1
1
– 25
– 25
/2
/4
cyc
t
t
SPSCK
SPSCK
Unit
t
t
t
t
t
t
Hz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
cyc
cyc
cyc
cyc
31

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