TINY12 ATMEL [ATMEL Corporation], TINY12 Datasheet - Page 38

• Manufacturer Part Number: TINY12
• Description: 8-bit AVR Microcontroller with 1K Byte Flash
• Manufacturer: ATMEL [ATMEL Corporation]

ATtiny12 EEPROM
Read/Write Access
EEPROM Address Register –
EEAR
EEPROM Data Register –
EEDR
EEPROM Control Register –
EECR
38
ATtiny11/12
The EEPROM access registers are accessible in the I/O space.
The write access time is in the range of 3.1 - 6.8 ms, depending on the frequency of the
calibrated RC oscillator. See Table 17 for details. A self-timing function lets the user
software detect when the next byte can be written. A special EEPROM Ready interrupt
can be set to trigger when the EEPROM is ready to accept new data. The minimum volt-
age for writing to the EEPROM is 2.2V.
In order to prevent unintentional EEPROM writes, a two-state write procedure must be
followed. Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed. When the EEPROM is read, the CPU is halted for four clock
cycles before the next instruction is executed.
The EEPROM Address Register – EEAR specifies the EEPROM address in the 64-byte
EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 63.
During reset, the EEAR register is not cleared. Instead, the data in the register is kept.
• Bits 7..0 - EEDR7.0: EEPROM Data
For the EEPROM write operation, the EEDR register contains the data to be written to
the EEPROM in the address given by the EEAR register. For the EEPROM read opera-
tion, the EEDR contains the data read out from the EEPROM at the address given by
EEAR.
• Bit 7..4 - Res: Reserved Bits
These bits are reserved bits in the ATtiny12 and will always read as zero.
• Bit 3 - EERIE: EEPROM Ready Interrupt Enable
When the I-bit in SREG and EERIE are set (one), the EEPROM Ready interrupt is
enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready interrupt
generates a constant interrupt when EEWE is cleared (zero).
Bit
$1E
Read/Write
Initial Value
Bit
$1D
Read/Write
Initial Value
Bit
$1C
Read/Write
Initial Value
MSB
R/W
R
R
7
0
7
0
7
0
-
-
R/W
R
R
6
0
6
0
6
0
-
-
EEAR5
R/W
R/W
X
R
5
5
0
5
0
-
EEAR4
R/W
R/W
X
R
4
4
0
4
0
-
EEAR3
EERIE
R/W
R/W
R/W
X
3
3
0
3
0
EEMWE
EEAR2
R/W
R/W
R/W
X
2
2
0
2
0
EEAR1
EEWE
R/W
R/W
R/W
X
1
1
0
X
1
EEAR0
EERE
LSB
R/W
R/W
R/W
X
0
0
0
0
0
1006D–AVR–07/03
EECR
EEAR
EEDR