P89LPC920FDH PHILIPS [NXP Semiconductors], P89LPC920FDH Datasheet - Page 36

• Manufacturer Part Number: P89LPC920FDH
• Description: 8-bit microcontrollers with two-clock 80C51 core 2 kB/4 kB/8 kB 3 V low-power Flash with 256-byte data RAM
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
[2]
[3]
[4]
[5]
[6]
[7]
[8]
11. Dynamic characteristics
Table 9:
T
[1]
[2]
9397 750 12285
Product data
Symbol
f
f
f
t
f
Glitch filter
External clock
t
t
t
t
Shift register (UART mode 0)
t
t
t
t
t
RCOSC
WDOSC
OCS
CLCL
CLKP
CHCX
CLCX
CLCH
CHCL
XLXL
QVXH
XHQX
XHDX
DVXH
amb
The I
detect, and Watchdog timer.
See
V
Pin capacitance is characterized but not tested.
Measured with port in quasi-bidirectional mode.
Measured with port in high-impedance mode.
Ports in quasi-bidirectional mode with weak pull-up (applies to all port pins with pull-ups). Does not apply to open-drain pins.
Port pins source a transition current when used in quasi-bidirectional mode and externally driven from ‘1’ to ‘0’. This current is highest
when V
Parameters are valid over operating temperature range unless otherwise specified.
Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.
= 40 C to +85 C for industrial, unless otherwise specified.
OL
/V
Table 7 “Limiting values” on page 34
DD
OH
, I
IN
AC characteristics
Parameter
internal RC oscillator frequency
(nominal f = 7.3728 MHz)
internal Watchdog oscillator
frequency (nominal f = 400 kHz)
oscillator frequency
clock cycle
CLKLP active frequency
glitch rejection, P1.5/RST pin
signal acceptance, P1.5/RST pin
glitch rejection, any pin except
P1.5/RST
signal acceptance, any pin except
P1.5/RST
HIGH time
LOW time
rise time
fall time
serial port clock cycle time
output data set-up to clock rising
edge
output data hold after clock rising
edge
input data hold after clock rising edge
input data valid to clock rising edge
may exceed the related specification.
ID
is approximately 2 V.
, and I
PD
specifications are measured using an external clock with the following functions disabled: comparators, brownout
for steady state (non-transient) limits on I
Rev. 06 — 21 November 2003
Conditions
trimmed to 1%
at T
see
see
see
see
see
amb
Figure 13
Figure 13
Figure 13
Figure 13
Figure 13
= 25 C
[1]
8-bit microcontrollers with two-clock 80C51 core
Variable clock
Min
7.189
280
0
83
0
-
125
-
50
33
33
-
-
16 t
13 t
-
-
150
CLCL
CLCL
P89LPC920/921/922
OL
or I
OH
Max
7.557
480
12
-
8
50
-
15
-
t
t
8
8
-
-
t
0
-
CLCL
CLCL
CLCL
. If I
OL
+ 20
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
/I
t
t
OH
CLCX
CHCX
exceeds the test condition,
f
Min
7.189
280
-
-
-
-
125
-
50
33
33
-
-
1333
1083
-
-
150
OSC
= 12 MHz
Max
7.557
480
-
-
-
50
-
15
-
-
-
8
8
-
-
103
0
-
36 of 45
Unit
MHz
kHz
MHz
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns