TLE5012-E0318 INFINEON [Infineon Technologies AG], TLE5012-E0318 Datasheet - Page 29

• Manufacturer Part Number: TLE5012-E0318
• Description: GMR-Based Angular Sensor for Rotor Position Sensing
• Manufacturer: INFINEON [Infineon Technologies AG]

Data Communication via SSC
Figure 19
The data communication via SSC interface has the following characteristic:
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Cyclic Redundancy Check (CRC)
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Figure 20
Target Data Sheet
output
Serial
CRC
DATA
SCK
CSQ
The data transmission order is “Most Significant Bit (MSB) first”.
Data is put on the data line with the rising edge on SCK and read with the falling edge on SCK.
The SSC Interface is word-aligned. All functions are activated after each transmitted word.
A “high” condition on the negated Chip Select pin (CSQ) of the selected TLE5012 interrupts the transfer
immediately. The CRC calculator is automatically reset.
After changing the data direction, a delay (t
This is necessary for internal register access.
Every access to the TLE5012 with the number of data (ND) ≥ 1 is performed with address auto-increment.
At an overflow at address 3F
With ND = 0 no auto-increment is done and a continuously readout of the same address can be realized.
Afterwards no Safety Word is send and the transfer ends with high condition on CSQ.
After every data transfer with ND ≥ 1 the 16 bit Safety Word will be appended by the selected TLE5012.
At a rising edge of CSQ without data transfer before (no SCK-pulse), the update-registers are updated with
according values.
After sending the Safety Word the transfer ends. To start another data transfer, the CSQ has to be deselected
once for t
The SSC is default Push-Pull. The Push-Pull driver is only active, if the TLE5012 has to send data, otherwise
the Push-Pull is disabled for receiving data from the microcontroller.
This CRC is according to the J1850 Bus-Specification.
Every new transfer resets the CRC generation.
Every Byte of a transfer will be taken into account to generate the CRC (also the sent command(s)).
Generator-Polynomial: X8+X4+X3+X2+1, but for the CRC generation the fast-CRC generation circuit is used
(see
The remainder of the fast CRC circuit is initial set to ’11111111
Remainder is inverted before transmission.
Figure
RW
MSB
SSC Bit Ordering (Read Example)
Fast CRC Polynomial Division Circuit
CSoff
X7
SSC Transfer
20)
SSC -Master is driving DAT A
SSC -Slave is driving DAT A
.
1
14
X6
13
LOCK
1
Command Word
12
X5
1
H
11
the transfer continuous at address 00
X4
UPD
10
1
9
Remainder
xor
parallel
wr_delay
8
X3
1
7
ADDR
) has to be considered before continuing the data transfer.
29
6
xor
X2
5
1
B
4
’.
xor
H
3
.
X1
LENGTH
2
1
X0
1
1
LSB
t
wr_delay
MSB
&
V 0.46, 2009-09
xor
Specification
1
Data Word (s)
TLE5012
LSB
TX_CRC
Input