HIP6201 INTERSIL [Intersil Corporation], HIP6201 Datasheet - Page 6

• Manufacturer Part Number: HIP6201
• Manufacturer: INTERSIL [Intersil Corporation]

Detailed Functional Description
As shown in the Block Diagram, the HIP6200 has two
comparators which compare the voltage on the CAP pin to
the voltage on the SNS pin. The CAP voltage follows the
SNS voltage with an R-C delay which is user programmable
and also variable depending upon the state of the amplifiers.
Normally, resistor R
amplifiers are not active. R
(V
transient, when either amplifier is active, the switch in series
with R
sets the time constant. Since R
R
the inductor current slews. The CAP voltage waveform is
depicted in the Typical Application Diagrams.
Prior to the load transient, V
likewise V
applications because the DC-DC converter will be in an
energy-saving skip-cycle mode at light load currents. In this
mode, the output voltage ripple may be in excess of 2%
and could trip the HIP6200’s comparators if V
track V
power. When a fast load transient occurs, V
follows V
V
When the DeCAPitator is active, it either supplies current
from the P
this, a high-quality capacitor must be placed locally from
P
deal of bulk capacitance as well as high frequency
decoupling sprinkled across the application board. P
tied to the system 5V bus through an on-chip 10
This resistor helps isolate the system 5V from the
disturbances on P
The HIP6200 has a power-on reset function which ensures
that both V
allowing amplifier operation. There is also an EN(ABLE) pin,
allowing users to disable the HIP6200 if desired. An
overtemperature (OT) shutdown feature ensures that the
HIP6200 will not self-destruct from thermal overload. An OT
event will shutdown the chip until the junction temperature
decreases a few degrees below its trip point.
The DeCAPitator draws very little bias current (300 A
typical) when its amplifiers are inactive. When either
amplifier is active, the chip draws 15-30mA of bias current.
This current is mainly for the active high-speed amplifier and
lasts only for the duration of the on-time of the HIP6200.
Component Selection Guidelines
Bulk Output Capacitors
For a given converter design without the HIP6200 in the
target application, the number of output capacitors is
determined mainly by the output voltage regulation and
OUT
T1
VCC
CAP
, the DeCAPitator has time to source or sink current as
T1
) follows the SNS voltage (V
exceeds +1% or -1.5% of V
to GND. The system 5V bus typically has a good
SNS
OUT
opens and R
SNS
VCC
CC
. This would turn on the amplifiers and waste
and the DeCAPitator becomes active when
) closely. This is important in many portable
and CAP are at some minimum levels before
pin or sources current to PGND. Because of
VCC
T1
T2
is in parallel with R
.
alone (with the capacitor on CAP)
2-446
T1
CAP
is small and the CAP voltage
T2
follows V
is 20 times larger than
SNS
CAP
.
) closely. During a
T2
OUT
when the
CAP
CAP
(and
no longer
did not
resistor.
HIP6200, HIP6201
VCC
is
transient specifications. It is estimated that for a load
transient of 0-8A with a di/dt of 20A/ s, eleven 220 F, 0.1
low ESR tantalum capacitors are necessary to maintain
CPU core voltage regulation specifications. For identical
conditions with a HIP6200 employed, only five 100 F, 0.1
low ESR tantalums are required. Similar savings in output
capacitance can be achieved with other capacitor dielectric-
types.
The number of capacitors which can be eliminated on the
output is limited by either of the following:
P
A 100 F, 0.1 tantalum is recommended on the P
for an application which has 8A transients (maximum
recommended operation of the HIP6200). R
internal 10 resistor from V
P
CAP Capacitor
The capacitor on the CAP pin sets the amount of time that
the HIP6200 has to sink or source current in response to a
load transient. The DeCAPitator on-time should be greater
than the converter response time. When the HIP6200’s
amplifiers are not active, the CAP pin follows the output
voltage closely to prevent false tripping at light loads due to
PWM skip-cycle modes of operation. These two
boundaries are addressed with R
HIP6200 but must also be verified on each design.
The converter response time is the time interval required for
the inductor current to slew to the output load current. This
time is dramatically different for the two edges of the
transient event if there is a large differential between input
and output voltages of the converter. The converter
response times are approximated by v = L*di/dt:
T
T
where
T
T
1. Output voltage ripple - this increases proportional to the
2. Leading edge voltage spike - this may increase with re-
R1
R2
R1
R2
VCC
VCC
=
=
equivalent ESR of the bulk output capacitance. This may
be counteracted by increasing the output inductance. In
many cases the inductor can remain the same because
the output ripple will still be acceptably small.
duced number of capacitors. The HIP6200 and its very
fast response is very effective in handling this leading
edge spike up to a point. Some additional ceramic decou-
pling on the OUT pin can also help.
= converter response time to low-to-high load transient
= converter response time to high-to-low load transient
L
L
transient from the system 5V (V
Capacitor
OUT
OUT
------------------------------------
--------------------
I
V
V
STEP
IN
OUT
I
STEP
–
V
OUT
CC
to P
T1
VCC
and R
CC
which decouples the
).
T2
VCC
internal to the
is an
VCC
(EQ. 1)
(EQ. 2)
pin