FAN53168MTC FAIRCHILD [Fairchild Semiconductor], FAN53168MTC Datasheet - Page 16

• Manufacturer Part Number: FAN53168MTC
• Description: 6-Bit VID Controlled 2-4 Phase DC-DC Controller
• Manufacturer: FAIRCHILD [Fairchild Semiconductor]

FAN53168
Power Good Monitoring
The Power Good comparator monitors the output voltage via
the CSREF pin. The PWRGD pin is an open drain output
whose high level (when connected to a pull-up resistor) indi-
cates that the output voltage is within the nominal limits
specified in the specifications above based on the VID volt-
age setting. PWRGD will go low if the output voltage is out-
side of this specified range. PWRGD is blanked during a
VID OTF event for a period of 250µs to prevent false signals
during the time the output is changing.
Output Crowbar
As part of the protection for the load and output components
of the supply, the PWM outputs will be driven low (turning
on the low-side MOSFETs) when the output voltage exceeds
the upper Power Good threshold. This crowbar action will
stop once the output voltage has fallen below the release
threshold of approximately 450mV.
Turning on the low-side MOSFETs pulls down the output as
the reverse current builds up in the inductors. If the output
overvoltage is due to a short of the high side MOSFET, this
action will current limit the input supply or blow its fuse,
protecting the microprocessor from destruction.
Output Enable and UVLO
The input supply (VCC) to the controller must be higher than
the UVLO threshold and the EN pin must be higher than its
logic threshold for the FAN53168 to begin switching. If
UVLO is less than the threshold or the EN pin is a logic low,
the FAN53168 is disabled. This holds the PWM outputs at
ground, shorts the DELAY capacitor to ground, and holds
the ILIMIT pin at ground.
In the application circuit, the ILIMIT pin should be con-
nected to the OD# pins of the FAN53418 drivers. Because
ILIMIT is grounded, this disables the drivers such that both
DRVH and DRVL are grounded. This feature is important to
prevent discharging of the output capacitors when the
16
Figure 4. VID On-the-Fly Waveforms, Circuit of Figure 1,
VID Change = 5mV, 5µs, 50 steps,
I
OUT
Change = 5A to 65A
controller is shut off. If the driver outputs were not disabled,
then a negative voltage could be generated on the output due
to the high current discharge of the output capacitors through
the inductors.
APPLICATION INFORMATION
The design parameters for a typical Intel VRD10-compliant
CPU application are as follows:
• Input voltage (V
• VID setting voltage (V
• Duty cycle (D) = 0.125
• Nominal output voltage at no load (V
• Nominal output voltage at 65 A load (V
•
• (V
• Maximum Output Current (I
•
• Number of Phases (n) = 3
• Switching frequency per phase (f
Setting the Clock Frequency
Soft-Start and Current Limit Latch-Off Delay Times
C
R
DLY
T
=
D
--------------------------------------------------------------------------
(
=
) = V
n f



×
20µA
ONL
SW
×
–
– V
5.83pF
Ω
-----------------------
2 R
IN
OFL
1
×
V
) = 12 V
VID
DLY
Ω
= 1.480 V – 1.3955 V = 84.5 mV
)
VID
–



----------------- -
1.5MΩ
×
) = 1.500 V
1
----------- -
V
O
t
SS
VID
) = 65 A
PRODUCT SPECIFICATION
∆
SW
) = 228 kHz
ONL
OFL
REV. 1.0.0 6/9/03
) = 1.480 V
Ω
) = 1.3955 V
Ω