DM9308J NSC [National Semiconductor], DM9308J Datasheet - Page 3

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DM9308J

Manufacturer Part Number
DM9308J
Description
Dual 4-Bit Latch
Manufacturer
NSC [National Semiconductor]
Datasheet
Functional Description
Data can be entered into the latch when both of the enable
inputs are LOW As long as this logic condition exists the
output of the latch will follow the input If either of the enable
inputs goes HIGH the data present in the latch at that time
is held in the latch and is no longer affected by data input
The master reset overrides all other input conditions and
forces the outputs of all the latches LOW when a LOW sig-
nal is applied to the Master Reset input
Logic Diagram
Switching Characteristics
Symbol
t
t
t
t
t
PLH
PHL
PLH
PHL
PHL
Propagation Delay
En to Qn
Propagation Delay
Dn to Qn
Propagation Delay
MR to Qn
Parameter
V
CC
e a
5 0V T
A
e a
3
Truth Table
Q
Q
H
L
X
25 C (See Section 5 for test waveforms and output load )
n
n
e
e
e
b
MR
Min
e
H
H
H
H
H
L
1
LOW Voltage Level
Immaterial
HIGH Voltage Level
e
Present Output State
Previous Output State
C
R
E0
L
L
H
H
X
L
L
L
9308
e
e
15 pF
400
E1
H
H
X
L
L
L
Max
30
22
15
18
22
D
H
X
X
X
X
L
Qn
Qn
Qn
Qn
H
L
L
b
b
b
1
1
1
Operation
Data Entry
Data Entry
Hold
Hold
Hold
Reset
Units
TL F 10208– 3
ns
ns
ns

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