ADP3810AR-42 AD [Analog Devices], ADP3810AR-42 Datasheet - Page 16

• Manufacturer Part Number: ADP3810AR-42
• Description: Secondary Side, Off-Line Battery Charger Controllers
• Manufacturer: AD [Analog Devices]

Step 14. Calculate value of R
Assuming that C
R3, reducing the loop gain. To calculate R
tor ratio to give an attenuation of 25.5 dB, which is a loss of 1/20.
To provide some margin in the circuit for gain fluctuations in
the various stages, the final value of R
300 .
Step 15. Calculate the value of C
To maintain high dc gain, a capacitor, C
ries with R
close to f
The pole frequency due to C
as:
Step 16. Check the current loop phase margin:
ADP3810/ADP3811
arc tan
M
C
C2
CI
C2
180 arc tan
to provide a phase boost at crossover:
. The zero provided by this RC network should be
2
f
f
ZM
CI
C2
f
Z2
1
f
is a short, R
P2
arc tan
R
R
C2
2
C2
f
f
f
CI
P2
Z 2
2
C2
C
M
20 1
C2
1
C2
f
R3
f
1.9 kHz
C2
arc tan
CI
and R3 can now be calculated
P1
1.9 kHz 300
to realize G
115
forms a resistor divider with
C2
R3
:
arc tan
1k
C2
1
40 Hz
f
f
was adjusted down to
C2
CI
Z2
C2
0.1574 (4.00)
0.1497 (3.80)
0.0098 (0.25)
0.0040 (0.10)
, is connected in se-
, simply set the resis-
SEATING
LOSS
f
f
PLANE
arc tan
CI
Z 3
:
PIN 1
200 nF
Dimensions shown in inches and (mm).
0.1968 (5.00)
0.1890 (4.80)
0.0500
(1.27)
BSC
8
1
OUTLINE DIMENSIONS
f
8-Lead Small Outline IC
f
PM
CI
0.0192 (0.49)
0.0138 (0.35)
0.0688 (1.75)
0.0532 (1.35)
5
4
0.2440 (6.20)
0.2284 (5.80)
(SO-8)
–16–
0.0098 (0.25)
0.0075 (0.19)
The above formula subtracts the phase of each pole and adds
the phase of each zero. The poles and zeros come in pairs, f
calculated in Step 15 from C
due to the output filter cap; and f
the same pole that was calculated in Step 9, and f
recalculated with the addition of the internal 200
follows:
The final phase margin of 115 is more than adequate for a
stable current loop. In reality, higher order parasitic poles reduce
the phase margin to significantly less than 115 for a 1.9 kHz
crossover. The same was not the case for the voltage loop be-
cause the cross over frequency of 100 Hz was well below the
parasitic poles.
A PSpice analysis of the resulting loop gain and phase for the
values calculated is shown in Figure 33.
180
100
100
–50
Figure 33. Current Loop Gain/Phase Plots
8
0
50
0
0.0196 (0.50)
0.0099 (0.25)
0
0.01
0.0500 (1.27)
0.0160 (0.41)
f
Z 3
0.1
x 45
2
1
C
C1
C2
FREQUENCY – Hz
/R
1
10
PHASE MARGIN = 105
C2
R
P1
C1
; f
/f
PM
Z3
100
R6
/f
due to C
ZM
calculated in Step 10
0dB CROSSOVER
1k
78 Hz
C1
10k
Z3
/R
needs to be
resistor as
C1
. f
100k
REV. 0
P1
P2
is
/f
Z2