ADP3168JRUZ-REEL AD [Analog Devices], ADP3168JRUZ-REEL Datasheet - Page 18

• Manufacturer Part Number: ADP3168JRUZ-REEL
• Description: 6-Bit, Programmable 2-, 3-, 4-Phase Synchronous Buck Controller
• Manufacturer: AD [Analog Devices]

ADP3168
POWER MOSFETS
For this example, the N-channel power MOSFETs have been
selected for one high-side switch and two low-side switches per
phase. The main selection parameters for the power MOSFETs
are V
voltage (the supply voltage to the ADP3418) dictates whether
standard threshold or logic-level threshold MOSFETs must be
used. With V
<2.5 V) are recommended.
The maximum output current I
ment for the low-side (synchronous) MOSFETs. The ADP3168,
balances currents between phases, thus the current in each low-
side MOSFET is the output current divided by the total number
of MOSFETs (n
following expression shows the total power being dissipated in
each synchronous MOSFET in terms of the ripple current per
phase (I
Knowing the maximum output current being designed for and
the maximum allowed power dissipation, one can find the
required R
an ambient temperature of 50°C, a safe limit for PSF is 1 W to
1.5 W at 120°C junction temperature. Thus, for this example
(65 A maximum), we find R
This R
so we need to make sure we account for this when making
this selection. For this example, we selected two lower-side
MOSFETs at 7 mΩ each at room temperature, which gives
8.4 mΩ at high temperature.
Another important factor for the synchronous MOSFET is
the input capacitance and feedback capacitance. The ratio
of the feedback to input needs to be small (less than 10%
is recommended) to prevent accidental turn-on of the
synchronous MOSFETs when the switch node goes high.
Also, the time to switch the synchronous MOSFETs off should
not exceed the nonoverlap dead time of the MOSFET driver
(40 ns typical for the ADP3418). The output impedance of
the driver is about 2 Ω and the typical MOSFET input gate
resistances are about 1 Ω to 2 Ω, so a total gate capacitance of
less than 6000 pF should be adhered to. Because there are
two MOSFETs in parallel, the input capacitance for each
synchronous MOSFET should be limited to 3000 pF.
The high-side (main) MOSFET must be able to handle two
main power dissipation components: conduction and switching
losses. The switching loss relates to the amount of time it takes
for the main MOSFET to turn on and off, and to the current
and voltage that are being switched. Basing the switching speed
on the rise and fall time of the gate driver impedance and
P
GS(TH)
SF
DS(SF)
R
) and average total output current (I
=
, Q
DS(ON)
(
is also at a junction temperature of about 120°C,
1
G
GATE
−
, C
D
SF
for the MOSFET. For D-PAK MOSFETs up to
ISS
). With conduction losses being dominant, the
)
~10 V, logic-level threshold MOSFETs (V
×
, C
⎡
⎢
⎢
⎣
⎛
⎜
⎜
⎝
RSS
n
I
, and R
SF
O
⎞
⎟
⎟
⎠
2
DS(SF)
+
DS(ON)
O
12
1
(per MOSFET) < 8.7 mΩ.
determines the R
×
. The minimum gate drive
⎛
⎜
⎜
⎝
n
n
SF
I
R
⎞
⎟
⎟
⎠
2
O
⎤
⎥
⎥
⎦
):
×
R
DS(ON)
DS
( )
SF
require-
(15)
GS(TH)
Rev. B | Page 18 of 24
MOSFET input capacitance, the following expression provides
an approximate value for the switching loss per main MOSFET,
where n
Here, R
about 1 Ω for typical high speed switching MOSFETs, making
R
MOSFET. Note that adding more main MOSFETs (n
not really help the switching loss per MOSFET because the
additional gate capacitance slows switching. The best thing to
reduce switching loss is to use lower gate capacitance devices.
The conduction loss of the main MOSFET is given by the
following, where R
Typically, for main MOSFETs, the highest speed (low C
device is preferred, but these usually have higher ON resistance.
Select a device that meets the total power dissipation (about
1.5 W for a single D-PAK) when combining the switching and
conduction losses.
For this example, an Infineon IPD12N03L was selected as the
main MOSFET (three total; n
(max) and R
Infineon IPD06N03L was selected as the synchronous
MOSFET (six total; n
R
MOSFET C
Solving for the power dissipation per MOSFET at I
I
1.44 W for each main MOSFET. These numbers work well
considering there is usually more PCB area available for each
main MOSFET vs. each synchronous MOSFET.
Also shown is the standby dissipation factor (I
the driver. For the ADP3418, the maximum dissipation should
be less than 400 mW. For our example, with I
Q
driver, which is below the 400 mW dissipation limit. See the
ADP3418 data sheet for more details.
One last thing to consider is the power dissipation in the driver
for each phase. This is best described in terms of the Q
MOSFETs and is given by the following, where Q
gate charge for each main MOSFET and Q
charge for each synchronous MOSFET:
R
P
G
DS(SF)
GMF
DRV
= 8.2 A yields 863 mW for each synchronous MOSFET and
= 3 Ω) and C
P
P
= 22.8 nC, and Q
= 8.4 mΩ (max at T
=
C
S
(
G
(
MF
MF
MF
⎡
⎢
⎣
is the total gate resistance (2 Ω for the ADP3418 and
2
f
is the total number of main MOSFETs:
)
)
×
SW
ISS
= 2
=
DS(MF)
n
D
is less than 3000 pF, satisfying that requirement.
×
×
ISS
×
(
= 14 mΩ (max at T
f
⎡
⎢
⎢
⎣
n
is the input capacitance of the main
DS(MF)
SW
⎛
⎜
⎜
⎝
MF
n
SF
I
MF
×
O
GSF
×
= 6), with C
V
is the ON resistance of the MOSFET:
Q
⎞
⎟
⎟
⎠
CC
= 34.3 nC, we find 260 mW in each
J
2
GMF
n
= 120°C). The synchronous
MF
+
×
MF
12
I
1
+
O
= 3), with a C
n
×
×
SF
⎛ ×
⎜
⎜
⎝
ISS
R
n
×
J
G
n
= 2370 pF (max) and
= 120°C), and an
Q
MF
×
I
GSF
R
n
GSF
MF
n
⎞
⎟
⎟
⎠
)
2
+
CC
⎤
⎥
⎥
⎦
ISS
is the total gate
CC
×
×
I
= 7 mA,
CC
C
= 1460 pF
R
× V
GMF
ISS
DS
⎤
⎥
⎦
O
×
(
MF
= 65 A and
CC
MF
is the total
V
) does
) for
G
ISS
CC
)
for the
(16)
(17)
)
(18)