XC17256DDD8M XILINX [Xilinx, Inc], XC17256DDD8M Datasheet

XC17256DDD8M

Manufacturer Part Number

XC17256DDD8M

Description

QPRO Family of XC1700D QML Configuration PROMs

Manufacturer

XILINX [Xilinx, Inc]

Datasheet

1.XC17256DDD8M.pdf (10 pages)

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DS070 (v2.1) June 1, 2000

Features

•

DS070 (v2.1) June 1, 2000

Product Specification

Certified to MIL-PRF-38535 Appendix A QML

(Qualified Manufacturer Listing.)

Also available under the following Standard Microcircuit

Drawings (SMD): 5962-94717 and 5962-95617.

Configuration one-time programmable (OTP) read-only

memory designed to store configuration bitstreams of

Xilinx FPGA devices

On-chip address counter, incremented by each rising

edge on the clock input

Simple interface to the FPGA requires only one user

I/O pin

Cascadable for storing longer or multiple bitstreams

Programmable reset polarity (active High or active

Low) for compatibility with different FPGA solutions

Low-power CMOS EPROM process

Available in 5V version only

Programming support by leading programmer

manufacturers.

Design support using the Xilinx Alliance and

Foundation series software packages.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

RESET/

RESET

OE/

Figure 1: Simplified Block Diagram (does not show programming circuit)

CLK

V CC

V PP

GND

www.xilinx.com

1-800-255-7778

Address Counter

EPROM

Matrix

Cell

QPRO Family of XC1700D QML

Configuration PROMs

Product Specification

Description

The XC1700D QPRO™ family of configuration PROMs pro-

vide an easy-to-use, cost-effective method for storing Xilinx

FPGA configuration bitstreams.

When the FPGA is in Master Serial mode, it generates a

configuration clock that drives the PROM. A short access

time after the rising clock edge, data appears on the PROM

DATA output pin that is connected to the FPGA D

FPGA generates the appropriate number of clock pulses to

complete the configuration. Once configured, it disables the

PROM. When the FPGA is in Slave Serial mode, the PROM

and the FPGA must both be clocked by an incoming signal.

Multiple devices can be concatenated by using the CEO

output to drive the CE input of the following device. The

clock inputs and the DATA outputs of all PROMs in this

chain are interconnected. All devices are compatible and

can be cascaded with other members of the family.

For device programming, either the Xilinx Alliance™ or the

Foundation™ series development systems compiles the

FPGA design file into a standard HEX format which is then

transferred to most commercial PROM programmers.

Output

CEO

DATA

DS027_01_021500

pin. The

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XC17256DDD8M Summary of contents

Page 1

R DS070 (v2.1) June 1, 2000 Features • Certified to MIL-PRF-38535 Appendix A QML (Qualified Manufacturer Listing.) • Also available under the following Standard Microcircuit Drawings (SMD): 5962-94717 and 5962-95617. • Configuration one-time programmable (OTP) read-only memory designed to store ...

Page 2

QPRO Family of XC1700D QML Configuration PROMs Pin Description DATA Data output, 3-stated when either are inactive. During programming, the DATA pin is I/O. Note that OE can be programmed to be either active High or active ...

Page 3

R Controlling PROMs Connecting the FPGA device with the PROM. • The DATA output(s) of the PROM(s) drives the D input of the lead FPGA device. • The Master FPGA CCLK output drives the CLK input(s) of the PROM(s). • ...

Page 4

QPRO Family of XC1700D QML Configuration PROMs Vcc DOUT FPGA MODES* RESET RESET CCLK DONE * For mode pin connections, refer to the appropriate FPGA data sheet. (Low Resets the Address Pointer) CCLK (Output) DIN DOUT (Output) Figure 2: Master ...

Page 5

R Standby Mode The PROM enters a low-power standby mode whenever CE is asserted High. The output remains in a high impedance state regardless of the state of the OE input. Table 1: Truth Table for XC1700 Control Inputs Control ...

Page 6

QPRO Family of XC1700D QML Configuration PROMs XC1736D, XC1765D, XC17128D and XC17256D Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Supply voltage relative to GND PP V Input voltage relative to GND IN V Voltage applied ...

Page 7

R AC Characteristics Over Operating Condition CE RESET/OE CLK T CE DATA Symbol data delay data delay CE T CLK to data delay CAC T Data hold from CE, OE, or CLK OH ...

Page 8

QPRO Family of XC1700D QML Configuration PROMs AC Characteristics Over Operating Condition When Cascading RESET/OE CE CLK DATA CEO Symbol T CLK to data float delay CDF (3) T CLK to CEO delay OCK ( CEO delay ...

Page 9

... R Ordering Information Device Number XC1736D XC1765D XC17128D XC17256D Valid Ordering Combinations XC17128DDD8M XC17256DDD8M 5962-9561701MPA Marking Information Due to the small size of the PROM package, the complete ordering part number cannot be marked on the package. Device Number XC1736D XC1765D XC17128D XC17256D Revision History The following table shows the revision history for this document ...

Page 10

QPRO Family of XC1700D QML Configuration PROMs 10 www.xilinx.com 1-800-255-7778 R DS070 (v2.1) June 1, 2000 Product Specification ...

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