IS93C56-3G ISSI [Integrated Silicon Solution, Inc], IS93C56-3G Datasheet - Page 2

• Manufacturer Part Number: IS93C56-3G
• Description: 2,048-BIT SERIAL ELECTRICALLY ERASABLE PROM
• Manufacturer: ISSI [Integrated Silicon Solution, Inc]

IS93C56-3
PIN CONFIGURATION
8-Pin DIP
ENDURANCE AND DATA RETENTION
The IS93C56-3 is designed for applications requiring up to
100,000 programming cycles (WRITE, WRALL, ERASE and
ERAL). It provides 10 years of secure data retention, without
power after the execution of 100,000 programming cycles.
DEVICE OPERATION
The IS93C56-3 is controlled by seven 9-bit instructions.
Instructions are clocked in (serially) on the D
instruction begins with a logical “1” (the start bit). This is
followed by the opcode (2 bits), the address field (8 bits), and data,
if appropriate. The clock signal (SK) may be halted at any
time and the IS93C56-3 will remain in its last state. This allows
full static flexibility and maximum power conservation.
Read (READ)
The READ instruction is the only instruction that outputs
serial data on the D
address have been decoded, data is transferred from the
selected memory register into a 16-bit serial shift register.
(Please note that one logical “0” bit precedes the actual
16-bit output data string.) The output on D
during the low-to-high transitions of SK (see Figure 3).
2
PIN DESCRIPTIONS
CS
SK
D
D
NC
Vcc
GND
D
IN
OUT
OUT
D
CS
SK
IN
1
2
3
4
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Not Connected
Power
Ground
OUT
pin. After the read instruction and
8
7
6
5
VCC
NC
NC
GND
PIN CONFIGURATION
8-Pin JEDEC Small Outline “G”
VCC
OUT
IN
NC
CS
SK
pin. Each
changes
1
2
3
4
Low Voltage Read
The IS93C56-3 has been designed to ensure that data
read operations are reliable in low voltage environments.
The IS93C56-3 is guaranteed to provide accurate data
during read operations with Vcc as low as 2.7V.
Auto Increment Read Operations
In the interest of memory transfer operation applications,
the IS93C56-3 has been designed to output a continuous
stream of memory content in response to a single read
operation instruction. To utilize this function, the system
asserts a read instruction specifying a start location ad-
dress. Once the 16 bits of the addressed word have been
clocked out, the data in consecutively higher address
locations is output. The address will wrap around continu-
ously with CS HIGH until the chip select (CS) control pin is
brought LOW. This allows for single instruction data dumps
to be executed with a minimum of firmware overhead.
Write Enable (WEN)
The write enable (WEN) instruction must be executed
before any device programming (WRITE, WRALL, ERASE,
and ERAL) can be done. When Vcc is applied, this device
Integrated Silicon Solution, Inc. — 1-800-379-4774
8
7
6
5
NC
GND
D
D
OUT
IN
PIN CONFIGURATION
8-Pin JEDEC Small Outline “GR”
D
OUT
D
CS
SK
IN
1
2
3
4
ISSI
8
7
6
5
VCC
NC
NC
GND
04/26/01
Rev. G
®