AT49F1604-70TC ATMEL [ATMEL Corporation], AT49F1604-70TC Datasheet - Page 3

• Manufacturer Part Number: AT49F1604-70TC
• Description: 16-Megabit 1M x 16/2M x 8 5-volt Only Flash Memory
• Manufacturer: ATMEL [ATMEL Corporation]

powering down the device, or by pulsing the RESET pin
low and then bringing it back to V
pend/Resume commands will not work while in this mode;
if entered they will result in data being programmed into the
device. It is not recommended that the six byte code reside
in the software of the final product but only exist in external
programming code.
The BYTE pin controls whether the device data I/O pins
operate in the byte or word configuration. If the BYTE pin is
Block Diagram
Device Operation
READ: The AT49F16X4(T) is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins are
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus conten-
tion.
COMMAND SEQUENCES: When the device is first pow-
ered on it will be reset to the read or standby mode
depending upon the state of the control line inputs. In order
to perform other device functions, a series of command
sequences are entered into the device. The command
sequences are shown in the Command Definitions table
A0 - A19
Y-DECODER
X-DECODER
ADDRESS
BUFFER
LATCH
INPUT
CC
. Erase and Erase Sus-
OUTPUT
BUFFER
PLANE A SECTORS
COMPARATOR
I/O0 - I/O15/A-1
SECTORS
PLANE B
IDENTIFIER
REGISTER
REGISTER
Y-GATING
STATUS
DATA
BUFFER
INPUT
set at logic “1”, the device is in word configuration, I/O0-
I/O15 are active and controlled by CE and OE.
If the BYTE pin is set at logic “0”, the device is in byte con-
figuration, and only data I/O pins I/O0-I/O7 are active and
controlled by CE and OE. The data I/O pins I/O8-I/O14 are
tri-stated, and the I/O15 pin is used as an input for the LSB
(A-1) address function.
(I/O8 - I/O15 are don't care inputs for the command codes).
The command sequences are written by applying a low
pulse on the WE or CE input with CE or WE low (respec-
tively) and OE high. The address is latched on the falling
edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE. Standard
microprocessor write timings are used. The address loca-
tions used in the command sequences are not affected by
entering the command sequences.
RESET: A RESET input pin is provided to ease some sys-
tem applications. When RESET is at a logic high level, the
device is in its standard operating mode. A low level on the
RESET input halts the present device operation and puts
WRITE STATE
COMMAND
REGISTER
MACHINE
PROGRAM/ERASE
VOLTAGE SWITCH
CE
WE
OE
RESET
BYTE
VCC
GND
RDY/BUSY
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