TEA2029 STMICROELECTRONICS [STMicroelectronics], TEA2029 Datasheet - Page 8

• Manufacturer Part Number: TEA2029
• Description: APPLICATION NOTE
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

TEA2028 - TEA2029 APPLICATION NOTE
- In practice, at low amplitude video signals, it is
Figure 8
V.2.2 - Memorizing the sync pulse 50% value
The objective is to memorize the voltage corre-
sponding to 50% of the line sync pulse V
an external capacitor connected to Pin 26 (see
Figure 9).
The overall arrangement comprises two compara-
tors.
- Comparator C2 : delivers an output voltage ”V1”
- Comparator C3 : which delivers a constant output
Figure 9
8/46
recommended to insert a low-pass filter before
the ”C27” capacitor so as to attenuate the chromi-
nance sub-carrier and the noise components.
The aim is to reduce the phase variations of the
detected sync pulse and thus enhance the hori-
zontal scanning stability.
by comparing V
across two resistors.
current thereby maintaining on capacitor ”C26”,
the voltage V
to peak sync pulse.
Chroma
Burst
50%
S1
corresponding to 50% of peak
V
+ V
S1
V
+
CC
D
+
, V
2R
V
1k
D
26
i
and the voltage drop
1
220nF
V
1
D
27
C2
S1
x K
V
I
D
V
+
CC
i
R
by using
+
CC
V
N
I
26
C
C26
V
50%
During the line scanning, diode ”D” is reverse bi-
ased : V
current I
During sync pulse interval, V
diode ”D” begins conducting and thus :
V
been slightly discharged
C3 begins charging the capacitor until C2 is
brought to equilibrium.
At this time, I
thus V
and V
A high value C26 capacitor will thus memorize the
voltage level correspondingto 50% of the line sync.
pulse.
V.2.2.1 -
During the line scanning period (T
capacitor C26 will loose a charge equivalent to :
I
This energy must be recovered before the end of
sync pulse such that : I
therefore
In practice, for C26 = 100nF, I
I
D
C
1
(T
= 800 A.
= (V
V
H
S1
V
N
1
1
- T
+
V
V
V
+
P
= V
= V
50%
50%
V
50%
D
V
V
I
S1
I
I
S
V
26
26
+ V
0
0
0
C
D
D
1
I
I
which will discharge the capacitor.
).
D
C
D
26
P
+ V
Ratio calculation
V
D
1
+ V
P
I
) - (2 R i
D
T
=
D
+
H
V
2
D
i
t
V
= V
S
26
D
I
= 2
where i =
C
t
t
S
=
S
1
2
V
< V
i
1
C
). Since the capacitor has
P
= V
I
I
2
C
D
t
26
S
V
P
V
> I
V
and C3 will deliver a
N
+ V
S1
1
12.6
26
D
+ V
> V
+ V
(T
N
D
D
V
t
t
t
t
R
+ 2 V
H
26
D
= V
D
= 25 A and
- T
, comparator
H
= V
- T
S
50%
V
D
)
N
- V
P
S
), the
+ V
26
D,