HCTL-2000_06 AVAGO [AVAGO TECHNOLOGIES LIMITED], HCTL-2000_06 Datasheet - Page 5

• Manufacturer Part Number: HCTL-2000_06
• Description: Quadrature Decoder/Counter Interface ICs
• Manufacturer: AVAGO [AVAGO TECHNOLOGIES LIMITED]

Switching Characteristics
Table 5. Switching Characteristics Min/Max specifications at V
Notes:
1. t
2. t
Figure 3. Tri-State Output Timing.
5
and hold times do not need to be observed.
10
11
12
13
14
15
16
17
18
19
20
21
CD
SS
1
2
3
4
5
6
7
8
9
, t
specification and waveform assume latch not inhibited.
OS
t
t
, t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
UDCH
UDCS
CD
OH
OS
SH
CHH
SS
UDD
UDH
ODE
CLH
DCD
DOD
CHD
CLK
ODZ
SDV
RST
DSD
CLD
SH
[2]
[1]
[2]
[2]
[2]
, t
OH
only pertain to proper operation of the inhibit logic. In other cases, such as 8 bit read operations, these setup
Clock period
Pulse width, clock high
Delay time, rising edge of clock to valid, updated count
information on D0-7
Delay time, OE fall to valid data
Delay time, OE rise to Hi-Z state on D0-7
Delay time, SEL valid to stable, selected data byte
(delay to High Byte = delay to Low Byte)
Pulse width, clock low
Setup time, SEL before clock fall
Setup time, OE before clock fall
Hold time, SEL after clock fall
Hold time, OE after clock fall
Pulse width, RST low
Hold time, last position count stable on D0-7 after clock rise
Hold time, last data byte stable after next SEL state change
Hold time, data byte stable after OE rise
Delay time, U/D valid after clock rise
Delay time, CNT
Delay time, CNT
Hold time, U/D stable after clock rise
Setup time, U/D valid before CNT
Hold time, U/D stable after CNT
Symbol Description
DCDR
DCDR
or CNT
or CNT
CAS
CAS
DCDR
high after clock rise
low after clock fall
DCDR
or CNT
or CNT
CAS
CAS
rise
rise
DD
= 5.0
5%, T
t
t
CLK
CLK
Min.
70
28
28
20
20
28
10
10
0
0
5
5
A
-45
-45
= -40 to + 85 C.
Max.
65
65
40
65
45
45
45
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns