SSTUG32868ET NXP [NXP Semiconductors], SSTUG32868ET Datasheet

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SSTUG32868ET

Manufacturer Part Number
SSTUG32868ET
Description
1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applications
Manufacturer
NXP [NXP Semiconductors]
Datasheet

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Part Number
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Part Number:
SSTUG32868ET/G,518
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
SSTUG32868ET/S,518
Manufacturer:
NXP Semiconductors
Quantity:
10 000
1. General description
2. Features
The SSTUG32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank
by four (2R
is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the
functionality of the normally required two registers in a single package, thereby freeing up
board real-estate and facilitating routing to accommodate high-density Dual In-line
Memory Module (DIMM) designs.
The SSTUG32868 also integrates a parity function, which accepts a parity bit from the
memory controller, compares it with the data received on the D-inputs and indicates
whether a parity error has occurred on its open-drain QERR pin (active LOW).
It further offers added features over the JEDEC standard register in that it is permanently
configured for high output drive strength. This allows use in high density designs with
heavier than normal net loading conditions. Furthermore, the SSTUG32868 features two
additional chip select inputs, which allow more versatile enabling and disabling in densely
populated memory modules. Both added features (drive strength and chip selects) are
fully backward compatible to the JEDEC standard register. Finally, the SSTUG32868 is
optimized for the fastest propagation delay in the SSTU family of registers.
The SSTUG32868 is packaged in a 176-ball, 8
fine-pitch ball grid array (TFBGA) package, which (while requiring a minimum
6 mm
conventional card technology.
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SSTUG32868
1.8 V 28-bit 1 : 2 configurable registered buffer with parity for
DDR2-1G RDIMM applications
Rev. 01 — 23 April 2007
28-bit data register supporting DDR2
Fully compliant to JEDEC standard for SSTUB32868
Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two
JEDEC-standard DDR2 registers (that is, 2
Parity checking function across 22 input data bits
Parity out signal
Controlled multi-impedance output impedance drivers enable optimal signal integrity
and speed
Meets or exceeds SSTUB32868 JEDEC standard speed performance
Supports up to 450 MHz clock frequency of operation
Permanently configured for high output drive
Optimized pinout for high-density DDR2 module design
Chip-selects minimize power consumption by gating data outputs from changing state
15 mm of board space) allows for adequate signal routing and escape using
4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It
SSTUA32864 or 2
22 grid, 0.65 mm ball pitch, thin profile
Product data sheet
SSTUA32866)

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SSTUG32868ET Summary of contents

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SSTUG32868 1.8 V 28-bit configurable registered buffer with parity for DDR2-1G RDIMM applications Rev. 01 — 23 April 2007 1. General description The SSTUG32868 is a 1.8 V 28-bit register specifically designed for use ...

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... SSTUG32868ET/S Pb-free (SnAgCu solder ball compound) 4.1 Ordering options Table 2. Type number SSTUG32868ET/G SSTUG32868ET/S SSTUG32868_1 Product data sheet 1.8 V DDR2-1G configurable registered buffer with parity 15 mm, 0.65 mm ball pitch TFBGA package Package Name Description TFBGA176 plastic thin fine-pitch ball grid array package; ...

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NXP Semiconductors 5. Functional diagram RESET VREF DCKE0, DCKE1 DODT0, DODT1 DCS0 CSGEN DCS1 DCS2 DCS3 (1) Register A configuration ( D5, D7 D12, D17 to D28 Fig 1. Logic diagram of SSTUG32868 (positive ...

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NXP Semiconductors RESET CK CK (1) Dn VREF PAR_IN DCS0 CSGEN DCS1 DCS2 DCS3 (1) Register A configuration ( D5, D7 D12, D17 to D28 (2) Register A configuration (C = 0): Q1A to ...

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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 3. Pin configuration for TFBGA176 SSTUG32868_1 Product data sheet 1.8 V DDR2-1G configurable registered buffer with parity SSTUG32868ET/G SSTUG32868ET/S ball A1 index area ...

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NXP Semiconductors Fig 4. Ball mapping ( Register SSTUG32868_1 Product data sheet ...

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NXP Semiconductors Fig 5. Ball mapping ( Register SSTUG32868_1 Product data sheet ...

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NXP Semiconductors 6.2 Pin description Table 3. Pin description Symbol Pin Register Ungated inputs DCKE0 D1 DCKE1 C1 DODT0 N1 DODT1 P1 Chip Select gated inputs D1 to A2, A1, B2, B1, C2, ...

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NXP Semiconductors Table 3. Pin description …continued Symbol Pin Register QCKE0A F2 QCKE0B H8 QCKE1A E2 QCKE1B F8 QODT0A N2 QODT0B M7 QODT1A P2 QODT1B M8 Output error QERR M3 Parity input PAR_IN ...

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NXP Semiconductors Table 3. Pin description …continued Symbol Pin Register GND A4, A6, C3, C4, C5, C6, E3, E4, E5, E6, G3, G4, G5, G6, J3, J4, J5, J6, L4, L5, L6, N3, ...

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NXP Semiconductors Table 5. Parity and standby function table [1] RESET DCS0 DCS1 floating X or floating ...

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NXP Semiconductors during the time from the LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the design of the SSTUG32868 must ensure that the outputs will remain LOW, thus ensuring no glitches on the output. The SSTUG32868 ...

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NXP Semiconductors 7.3 Register timing RESET CSGEN DCSn CK CK Dn, DODTn, (1) DCKEn Qn, QODTn, QCKEn (1) PAR_IN (2) QERR HIGH, LOW, or Don't care (1) After RESET is switched from LOW to HIGH, all data and PAR_IN input ...

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NXP Semiconductors RESET CSGEN DCSn CK CK Dn, DODTn, DCKEn Qn, QODTn, QCKEn PAR_IN (1) QERR unknown input event (1) If the data is clocked in on the m clock pulse, and PAR_IN is clocked ...

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NXP Semiconductors RESET (1) CSGEN (1) DCSn (1) CK (1) CK Dn, DODTn, (1) DCKEn Qn, QODTn, QCKEn (1) PAR_IN QERR (1) After RESET is switched from HIGH to LOW, all data and clock input signals must be held at ...

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... Human Body Model (HBM); 1 100 pF Machine Model (MM 200 pF Conditions [1] Dn and PAR_IN inputs [1] Dn and PAR_IN inputs [1] [1] Dn and PAR_IN inputs [2] RESET, CSGEN [2] RESET, CSGEN CK, CK CK, CK operating in free air SSTUG32868ET/G SSTUG32868ET/S Rev. 01 — 23 April 2007 SSTUG32868 Min Max 0.5 +2.5 [1][2] 0.5 +2.5 [1][ ...

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NXP Semiconductors 10. Characteristics Table 8. Characteristics Over recommended operating conditions, unless otherwise noted. Symbol Parameter V HIGH-level output voltage OH V LOW-level output voltage OL I input current I I supply current DD I dynamic operating current DDD per ...

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NXP Semiconductors Table 9. Timing requirements Over recommended operating conditions, unless otherwise noted. Symbol Parameter f clock frequency clk t pulse duration W t differential inputs active ACT time t differential inputs inactive INACT time t set-up time su t ...

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NXP Semiconductors 11. Test information 11.1 Parameter measurement information for data output load circuit All input pulses are supplied by generators having the following characteristics: Pulse Repetition Rate (PRR) unless otherwise specified. The outputs are ...

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NXP Semiconductors Fig 12. Voltage waveforms; set-up and hold times Fig 13. Voltage waveforms; propagation delay times (clock to output) Fig 14. Voltage waveforms; propagation delay times (reset to output) SSTUG32868_1 Product data sheet 1.8 V DDR2-1G configurable registered buffer ...

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NXP Semiconductors 11.2 Data output slew rate measurement All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z (1) C Fig 15. Load circuit, HIGH-to-LOW slew measurement Fig 16. Voltage ...

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NXP Semiconductors 11.3 Error output load circuit and voltage measurement All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z (1) C Fig 19. Load circuit, error output measurements Fig ...

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NXP Semiconductors Fig 22. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to SSTUG32868_1 Product data sheet 1.8 V DDR2-1G configurable registered buffer with parity timing V ICR inputs t PLH output waveform 2 clock inputs Rev. 01 — ...

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NXP Semiconductors 12. Package outline TFBGA176: plastic thin fine-pitch ball grid array package; 176 balls; body 0.7 mm ball A1 index area ...

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NXP Semiconductors 13. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 13.1 Introduction to soldering Soldering ...

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NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including ...

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NXP Semiconductors Fig 24. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 14. Abbreviations Table 14. Acronym CMOS DDR2 DIMM DRAM LVCMOS PRR RDIMM ...

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NXP Semiconductors 16. Legal information 16.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...

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NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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