SSTUA32864EC/G NXP [NXP Semiconductors], SSTUA32864EC/G Datasheet

SSTUA32864EC/G

Manufacturer Part Number

SSTUA32864EC/G

Description

1.8 V configurable registered buffer for DDR2-667 RDIMM applications

Manufacturer

NXP [NXP Semiconductors]

Datasheet

1.SSTUA32864ECG.pdf (20 pages)

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1. General description

The SSTUA32864 is a 25-bit 1 : 1 or 14-bit 1 : 2 conﬁgurable registered buffer designed

for 1.7 V to 2.0 V V

All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The

control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized

to drive the DDR2 DIMM load.

The SSTUA32864 operates from a differential clock (CK and CK). Data are registered at

the crossing of CK going HIGH, and CK going LOW.

The C0 input controls the pinout conﬁguration of the 1 : 2 pinout from A conﬁguration

(when LOW) to B conﬁguration (when HIGH). The C1 input controls the pinout

conﬁguration from 25-bit 1 : 1 (when LOW) to 14-bit 1 : 2 (when HIGH).

The device supports low-power standby operation. When the reset input (RESET) is LOW,

the differential input receivers are disabled, and un-driven (ﬂoating) data, clock and

reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW all

registers are reset, and all outputs are forced LOW. The LVCMOS RESET and Cn inputs

must always be held at a valid logic HIGH or LOW level.

To ensure deﬁned outputs from the register before a stable clock has been supplied,

RESET must be held in the LOW state during power-up.

In the DDR2 RDIMM application, RESET is speciﬁed to be completely asynchronous with

respect to CK and CK. Therefore, no timing relationship can be guaranteed between the

two. When entering reset, the register will be cleared and the data outputs will be driven

LOW quickly, relative to the time to disable the differential input receivers. However, when

coming out of reset, the register will become active quickly, relative to the time to enable

the differential input receivers. As long as the data inputs are LOW, and the clock is stable

during the time from the LOW-to-HIGH transition of RESET until the input receivers are

fully enabled, the design of the SSTUA32864 must ensure that the outputs will remain

LOW, thus ensuring no glitches on the output.

The device monitors both DCS and CSR inputs and will gate the Qn outputs from

changing states when both DCS and CSR inputs are HIGH. If either DCS or CSR input is

LOW, the Qn outputs will function normally. The RESET input has priority over the DCS

and CSR control and will force the outputs LOW. If the DCS-control functionality is not

desired, then the CSR input can be hardwired to ground, in which case the setup time

requirement for DCS would be the same as for the other Dn data inputs.

The SSTUA32864 is available in a 96-ball, low proﬁle ﬁne-pitch ball grid array (LFBGA96)

package.

SSTUA32864

1.8 V conﬁgurable registered buffer for DDR2-667 RDIMM

applications

Rev. 02 — 9 March 2007

operation.

Product data sheet

Related parts for SSTUA32864EC/G

SSTUA32864EC/G Summary of contents

Page 1

SSTUA32864 1.8 V conﬁgurable registered buffer for DDR2-667 RDIMM applications Rev. 02 — 9 March 2007 1. General description The SSTUA32864 is a 25-bit 14-bit conﬁgurable registered buffer designed for 1 ...

Page 2

... Ordering information Table 1. Ordering information +70 C. amb Type number Solder process SSTUA32864EC/G Pb-free (SnAgCu solder ball compound) SSTUA32864EC SnPb solder ball compound SSTUA32864_2 Product data sheet 1.8 V conﬁgurable registered buffer for DDR2-667 RDIMM applications 5.5 mm, 0.8 mm ball pitch LFBGA package ...

Page 3

NXP Semiconductors 5. Functional diagram (1) Disabled conﬁguration. Fig 1. Functional diagram of SSTUA32864 mode (positive logic) SSTUA32864_2 Product data sheet 1.8 V conﬁgurable registered buffer for DDR2-667 RDIMM applications RESET CK CK ...

Page 4

... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. Pin conﬁguration for LFBGA96 Fig 3. Ball mapping register ( 0); top view SSTUA32864_2 Product data sheet 1.8 V conﬁgurable registered buffer for DDR2-667 RDIMM applications SSTUA32864EC/G ball A1 SSTUA32864EC index area ...

Page 5

NXP Semiconductors Fig 4. Ball mapping register A ( 1); top view Fig 5. Ball mapping register B ( 1); top view SSTUA32864_2 Product data sheet ...

Page 6

NXP Semiconductors 6.2 Pin description Table 2. Pin description Symbol Pin GND B3, B4, D3, D4, F3, F4, H3, H4, K3, K4, M3, M4, P3 A4, C3, C4, E3, E4, DD G3, G4, J3, J4, L3, L4, N3, ...

Page 7

NXP Semiconductors 7. Functional description 7.1 Function table Table LOW voltage level HIGH voltage level don’t care; = HIGH-to-LOW transition RESET ...

Page 8

NXP Semiconductors 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD V input voltage I V output voltage O I input clamping current IK I output ...

Page 9

NXP Semiconductors 10. Characteristics Table 6. Characteristics Recommended operating conditions; T unless otherwise speciﬁed. Symbol Parameter V HIGH-level output voltage OH V LOW-level output voltage OL I input current I I supply current DD I dynamic operating current DDD per ...

Page 10

NXP Semiconductors Table 7. Timing requirements Recommended operating conditions; T See Figure 6 through Figure 11. Symbol Parameter f clock frequency clock t pulse width W t differential inputs active time ACT t differential inputs inactive time INACT t set-up ...

Page 11

NXP Semiconductors 11. Test information 11.1 Test circuit All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z The outputs are measured one at a time with one transition per measurement. CK inputs (1) C ...

Page 12

NXP Semiconductors Fig 9. Voltage waveforms; setup and hold times Fig 10. Voltage waveforms; propagation delay times (clock to output) Fig 11. Voltage waveforms; propagation delay times (reset to output) SSTUA32864_2 Product data sheet 1.8 V conﬁgurable registered buffer for ...

Page 13

NXP Semiconductors 11.2 Output slew rate measurement All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z (1) C Fig 12. Load circuit, HIGH-to-LOW slew measurement Fig 13. Voltage waveforms, ...

Page 14

NXP Semiconductors 12. Package outline LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm ball A1 index area ...

Page 15

NXP Semiconductors 13. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow soldering description” . 13.1 Introduction to soldering Soldering ...

Page 16

NXP Semiconductors 13.4 Reﬂow soldering Key characteristics in reﬂow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including ...

Page 17

NXP Semiconductors Fig 17. Temperature proﬁles for large and small components For further information on temperature proﬁles, refer to Application Note AN10365 “Surface mount reﬂow soldering description” . 14. Abbreviations Table 12. Acronym CMOS DDR DIMM LVCMOS PRR RDIMM SSTL ...

Page 18

NXP Semiconductors 15. Revision history Table 13. Revision history Document ID Release date SSTUA32864_2 20070309 • Modiﬁcations: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have ...

Page 19

NXP Semiconductors 16. Legal information 16.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualiﬁcation Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...

Page 20

NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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