ADUC702X_1 AD [Analog Devices], ADUC702X_1 Datasheet
ADUC702X_1
Related parts for ADUC702X_1
ADUC702X_1 Summary of contents
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Preliminary Technical Data FEATURES Analog I/O Multi-Channel, 12-bit, 1MSPS ADC - ADC channels * Fully differential and single-ended modes Analog Input Range REF 12-bit Voltage Output DACs - DAC outputs available* ...
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ADuC702x Series TABLE OF CONTENTS ADuC702x—Specifications ............................................................ 3 Terminology ...................................................................................... 6 Absolute Maximum Ratings............................................................ 7 Ordering Guide............................................................................. 9 Pin function descriptions .............................................................. 10 General Description ....................................................................... 19 Overview of the ARM7TDMI core.......................................... 19 Memory organisation................................................................. 20 ADC circuit information ............................................................... ...
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Preliminary Technical Data ADUC702X—SPECIFICATIONS Table 1. (AV = IOV = 2 3 unless otherwise noted.) Parameter ADC CHANNEL SPECIFICATIONS ADC Powerup Time DC Accuracy 2, 3 Resolution Integral Nonlinearity 4 Integral Nonlinearity Differential Nonlinearity ...
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ADuC702x Series Parameter ANALOG OUTPUTS Output Voltage Range_0 Ouput Voltage Range_1 Output Voltage Range_2 Output Impedance DAC AC CHARACTERISTICS Voltage Output Settling Time Voltage Output Settling Time Digital to Analog Glitch Energy COMPARATOR Input Offset Voltage Input Bias Current Input ...
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Preliminary Technical Data Parameter 13 14 POWER REQUIREMENTS , Power Supply Voltage Range AV – AGND and IOV - IOGND DD DD Power Supply Current Normal Mode Power Supply Current Idle Mode Power Supply Current Power Down Mode 1 Temperature ...
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ADuC702x Series TERMINOLOGY ADC Specifications Integral Nonlinearity This is the maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1/2 ...
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Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS Table 2. Absolute Maximum Ratings (T Parameter AGND to DGND DV to DGND AGND DD DD Digital Input Voltage to DGND Digital Output Voltage to DGND VREF ...
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ADuC702x Series PIN CONFIGURATION 40-Lead CSP 40 PIN 1 1 IDENTIFIER TOP VIEW (Not to Scale 64-Lead CSP 64 PIN 1 1 IDENTIFIER ADuC7024/ADuC7025 TOP VIEW (Not to Scale ...
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Preliminary Technical Data ORDERING GUIDE Model ADC DAC Channels Channels ADuC7020BCP62 5 4 ADuC7021BCP62 8 2 ADuC7021BCP32 8 2 ADuC7021ACP32 8 (10 Bit 2 NMC) ADuC7022BCP62 10 ADuC7022BCP32 10 ADuC7022ACP32 10 (10 Bit NMC) ADuC7024BCP62 10 2 ADuC7024BST62 10 2 ...
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ADuC702x Series PIN FUNCTION DESCRIPTIONS – ADUC7020/ADUC7021/ADUC7022 Table 3. Pin Function Descriptions Pin# ADuC702X Mnemonic 7020 7021 7022 ADC0 ADC1 ADC2/CMP0 ADC3/CMP1 ADC4 - 2 ...
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Preliminary Technical Data Pin# ADuC702X Mnemonic 7020 7021 7022 XCLKO XCLKI P1.7/SPM7/PLAO P1.6/SPM6/PLAI[ P1.5/SPM5/PLAI[ P1.4/SPM4/PLAI[ P1.3/SPM3/PLAI[ ...
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ADuC702x Series PIN FUNCTION DESCRIPTIONS – ADUC7024/ADUC7025 Table 4. Pin Function Descriptions Pin# Mnemonic 1 ADC4 2 ADC5 3 ADC6 4 ADC7 5 ADC8 6 ADC9 7 GND REF 8 ADCNEG 9 DAC0**/ADC12 10 DAC1**/ADC13 11 TMS 12 TDI 13 ...
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Preliminary Technical Data Pin# Mnemonic 31 IRQ0/P0.4/CONV /PLAO[1] START 32 IRQ1/P0.5/ADC /PLAO[2] BUSY 33 P2.0/PWM /SPM9/PLAO[5]/CONV TRIP 34 P0.7/ECLK/SPM8/PLAO[4] 35 XCLKO 36 XCLKI 37 P3.6/PWM /PLAI[14] TRIP 38 P3.7/PWMSYNC/PLAI[15] 39 P1.7/SPM7/PLAO[0] 40 P1.6/SPM6/PLAI[6] 41 IOGND 42 IOV DD 43 P4.0/PLAO[8] ...
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ADuC702x Series Pin# Mnemonic 52 P4.3/PLAO[11] 53 P4.4/PLAO[12] 54 P4.5/PLAO[13 REF 56 DAC REF 57 DACGND 58 AGND DACV DD 61 ADC0 62 ADC1 63 ADC2/CMP0 64 ADC3/CMP1 * I = Input ...
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Preliminary Technical Data PIN FUNCTION DESCRIPTIONS – ADUC7026/ADUC7027 Table 5. Pin Function Descriptions Pin# Mnemonic 1 ADC4 2 ADC5 3 ADC6 4 ADC7 5 ADC8 6 ADC9 7 ADC10 8 GND REF 9 ADCNEG 10 DAC0/ADC12 11 DAC1/ADC13 12 DAC1/ADC14 ...
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ADuC702x Series Pin# Mnemonic 34 P0.3/TRST/A16/ADC BUSY 35 P2.5/MS1 36 P2.6/MS2 37 RST 38 P3.4/AD4/PWM2 /PLAI[12 P3.5/AD5/PWM2 /PLAI[13 IRQ0/P0.4/CONV /PLAO[1] START 41 IRQ1/P0.5/ADC /PLAO[2] BUSY 42 P2.0/PWM /SPM9/PLAO[5]/CONV TRIP 43 P0.7/ECLK/SPM8/PLAO[4] 44 XCLKO 45 XCLKI 46 ...
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Preliminary Technical Data Pin# Mnemonic 60 P1.2/SPM2/PLAI[2] 61 P1.1/SPM1/PLAI[1] 62 P1.0/T1/SPM0/PLAI[0] 63 P4.2/AD10/PLAO[10] 64 P4.3/AD11/PLAO[11] 65 P4.4/AD12/PLAO[12] 66 P4.5/AD13/PLAO[13] 67 REFGND 68 V REF 69 DAC REF 70 DACGND 71 AGND 72 AGND ...
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ADuC702x Series ADC0 ADC1 ADC2/CMP0 ADC3/CMP1 ADC4 ADC5 ADC 1MSPS ADC6 MUX ADC7 ADC8 ADC9 ADC10 ADC11 TEMP ADC NEG SENSOR MUX DAC CMP BM/P0.0/CMP /PLAO OUT V REF DAC MUX V REF BAND GAP REFERENCE SPI/I P4.6/PLAO/AD14 PROG. LOGIC ...
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Preliminary Technical Data GENERAL DESCRIPTION The ADuC702x is fully integrated, 1MSPS, 12-bit data acquisition system incorporating a high performance multi- channel ADC, a 16/32-bit MCU and Flash/EE Memory on a single chip. The ADC consists single-ended ...
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ADuC702x Series - Software interrupt (SWI) instruction which can be used to make a call to an operating system. Typically the programmer will define interrupts as IRQ but for higher priority interrupt, i.e. faster response time, the programmer can define ...
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Preliminary Technical Data Memory Access The ARM7 core sees memory as a linear array byte location where the different blocks of memory are mapped as outlined in . Figure 4 The ADuC702x memory organisation is configured in ...
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ADuC702x Series Table 6. Complete MMRs list Address Name Byte Access Type IRQ address base = 0xFFFF0000 0x0000 IRQSTA 4 R 0x0004 IRQSIG 4 R 0x0008 IRQEN 4 RW 0x000C IRQCLR 4 W 0x0010 SWICFG 4 W 0x0100 FIQSTA 4 ...
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Preliminary Technical Data Address Name Byte Access Type I2C0 base address = 0xFFFF0800 0x0800 I2C0MSTA 1 R 0x0804 I2C0SSTA 1 R 0x0808 I2C0SRX 1 R 0x080C I2C0STX 1 W 0x0810 I2C0MRX 1 R 0x0814 I2C0MTX 1 W 0x0818 I2C0CNT 1 ...
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ADuC702x Series 0xF404 GP1CON 4 RW 0xF408 GP2CON 4 RW 0xF40C GP3CON 4 RW 0xF410 GP4CON 4 RW 0xF420 GP0DAT 4 RW 0xF424 GP0SET 1 W 0xF428 GP0CLR 1 W 0xF430 GP1DAT 4 RW 0xF434 GP1SET 1 W 0xF438 GP1CLR ...
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Preliminary Technical Data ADC CIRCUIT INFORMATION GENERAL OVERVIEW The Analog Digital Converter (ADC) incorporates a fast, multi- channel, 12-bit ADC. It can operate from 2.7V to 3.6V supplies and is capable of providing a throughput 1MSPS when ...
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ADuC702x Series OUTPUT CODE 0111 1111 1111 2xV REF 1LSB = 0111 1111 1110 4096 0111 1111 1101 0000 0000 0001 0000 0000 0000 1111 1111 1111 1000 0000 0010 1000 0000 0001 1000 0000 0000 -V + 1LSB 0LSB ...
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Preliminary Technical Data 000 Enable CONV pin (pin 31 conversion input START 001 Enable timer1 as a conversion input 010 Enable timer0 as a conversion input 011 Single software conversion 100 Continuous software conversion 101 PLA conversion Other ...
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ADuC702x Series CONVERTER OPERATION The ADC incorporates a successive approximation (SAR) architecture involving a charge-sampled input stage. This architecture is described below for the three different modes of operation. Differential mode The ADuC702x contains a successive approximation ADC based on ...
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Preliminary Technical Data impedance source. Large source impedances will significantly affect the AC performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of the op amp will be a function of the particular ...
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ADuC702x Series Bit Description 7-2 Reserved 1 Internal reference output enable Cleared by user to place the internal reference in normal mode and use it for ADC conversions Set by user to place the internal reference in power-down mode and ...
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Preliminary Technical Data NONVOLATILE FLASH/EE MEMORY FLASH/EE MEMORY OVERVIEW The ADuC702x incorporates Flash/EE memory technology on- chip to provide the user with non-volatile, in-circuit reprogrammable memory space. Like EEPROM, Flash memory can be programmed in-system at a byte level, although ...
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ADuC702x Series FLASH/EE CONTROL INTERFACE Serial, parallel and JTAG programming use the Flash/EE Control Interface, which includes seven MMRs: - FEESTA: read only register, reflects the status of the Flash Control Interface - FEEMOD: sets the operating mode of the ...
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Preliminary Technical Data Mass erase Erase 62kByte of user space. The 2kByte of kernel are protected. This operation takes 2.48s To prevent 0x06* accidental execution a command sequence is required to execute this instruction, this is described below. 0x07 Burst ...
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ADuC702x Series cycle must also be added before fetching another instruction. Data transfer instruction are more complex and are summarised Table 16. Table 16: execution cycles in ARM/Thumb mode Instructions Fetch Dead Data access cycles time 2/1 ...
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Preliminary Technical Data RESET AND REMAP The ARM exception vectors are all situated at the bottom of the memory array, from address 0x00000000 to address 0x00000020 as shown Figure 16. kernel interrupt service routines 00080000h interrupt service routines 00010000h ARM ...
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ADuC702x Series OTHER ANALOG PERIPHERALS DAC The ADuC702x incorporate dual 12-bit voltage output DACs on-chip. Each DAC has a rail-to-rail voltage output buffer capable of driving 5kΩ/100pF. Each buffer can be bypassed. Each DAC has three selectable ranges ...
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Preliminary Technical Data Using the DACs The on-chip DAC architecture consists of a resistor string DAC followed by an output buffer amplifier, the functional equivalent of which is illustrated in Figure 17 REF BYPASSED FROM MCU R ...
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ADuC702x Series POWER SUPPLY MONITOR The Power Supply Monitor monitors the IOV ADuC702x. It indicate when IOV supply pin drops below one DD of two supply trip points. The monitor function is controlled via the PSMCON register. If enabled in ...
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Preliminary Technical Data 10 11 7-6 CMPOC Comparator output configuration bits CMPOL Comparator output logic state bit When low the comparator output is high when the positive input (CMP0) is above the negative input (CMP1). ...
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ADuC702x Series Bit Name Description 7-3 Reserved 2 SCLKS Slow clock selection for watchdog timer: Set by the user to use the internal 32kHz for the timer. This bit must be set to use watchdog timer if there is no ...
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Preliminary Technical Data DIGITAL PERIPHERALS THREE-PHASE PWM General overview The ADuC702x provides a flexible, programmable, three-phase PWM waveform generator that can be programmed to generate the required switching patterns to drive a three-phase voltage source inverter for ac induction (ACIM) ...
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ADuC702x Series high-side or the low-side output. In addition, the Output Control Unit allows individual enabling/disabling of each of the six PWM output signals. • The Gate Drive Unit permits the generation of the high frequency chopping frequency and its ...
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Preliminary Technical Data of the dead time can therefore be programmed in increments for a 47 MHz core clock). The PWMDAT1 CORE register is a 10-bit register so that its maximum value is 0x3FF (= ...
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ADuC702x Series symmetrical output patterns. Also shown is the PWMSYNC pulse and Bit 0 of the PWMSTA register that indicates whether operation is in the first or second half cycle of the PWM period. The resultant on-times of the PWM ...
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Preliminary Technical Data the Output Control Unit so that the signal appears at the 0H pin. Following a reset, the three crossover bits are cleared so that the crossover mode is disabled on all three pairs of PWM signals. The ...
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ADuC702x Series PWMCH0 PWMCH0 PWMDAT1 (GDCLK + CORE PWMDAT0 Figure 25: typical PWM signals with high frequency gate chopping enabled on both high-side and low-side switches PWM shutdown In the ...
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Preliminary Technical Data 8 PWMTRIPINT PWM trip interrupt bit 3 PWMTRIP Raw signal from the PWMTRIP pin 2-1 Reserved 0 PWMPHASE PWM Phase Bit Set to ‘1’ by the MicroConverter when the timer is counting down (1 Clear to ‘0’ ...
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ADuC702x Series GENERAL PURPOSE I/O The ADuC702x provides 40 General Purpose bi-directional I/O pins (GPIO). All I/O pins are 5V tolerant which means that the GPIOs support an input voltage of 5V. In general many of the GPIO pins have ...
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Preliminary Technical Data Bit Description 31-24 Direction of the data: Set to ‘1’ by the user to configure the GPIO pin as an output Clear to ‘0’ by the user to configure the GPIO pin as an input 23-16 Port ...
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ADuC702x Series SERIAL PORT MUX The Serial Port Mux multiplexes the serial port peripherals (two SPI, UART) and the Programmable Logic Array (PLA set of ten GPIO pins. Each pin must be configured to one ...
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Preliminary Technical Data 45 . 088 × × 3 2048 9600 019 M 2048 and N = 0.019 x 2048 = 088 = Baudrate ...
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ADuC702x Series Bit Name Description 7 Reserved 6 TEMT COMTX empty status bit Set automatically if COMTX is empty Cleared automatically when writing to COMTX 5 THRE COMTX and COMRX empty Set automatically if COMTX and COMRX are empty Cleared ...
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Preliminary Technical Data Bit Name Description 7-5 Reserved 4 LOOPBACK Loop back Set by user to enable loop back mode. In loop back mode the SOUT is forced high. Also the modem signals are directly connected to the status inputs ...
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ADuC702x Series Network addressable UART mode This mode allows connecting the MicroConverter on a 256- node serial network, either as a hardware single-master or via software in a multi-master network. Bit 7 of COMIEN1 (ENAM bit) must be set to ...
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Preliminary Technical Data SERIAL PERIPHERAL INTERFACE The ADuC702x integrates a complete hardware Serial Peripheral Interface (SPI) on-chip. SPI is an industry standard synchronous serial interface that allows eight bits of data to be synchronously transmitted and received simultaneously, i.e., full ...
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ADuC702x Series Cleared by user, the new serial byte received is discarded 7 SPITX underflow mode Set by user to transmit the previous data Cleared by user to transmit 0 6 Transfer and interrupt mode (master mode) Set by user ...
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Preliminary Technical Data COMPATIBLE INTERFACES The ADuC702x supports two fully licensed interfaces are both implemented as a full hardware master and 2 slave interface. The two I C interfaces being identical, this 2 document will describe only ...
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ADuC702x Series 3 General call enable bit Set by user to address every device on the I Cleared by user to operate in normal mode 2 Reserved 1 Master enable bit Set by user to enable the master I Cleared ...
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Preliminary Technical Data 4 No ACK Set automatically, if the master receive FIFO is full, the master doesn’t acknowledge the data received Cleared automatically 3 Master receive FIFO overflow Set automatically if the master receive FIFO is overflowing Cleared automatically ...
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ADuC702x Series PROGRAMMABLE LOGIC ARRAY (PLA) The ADuC702x integrates a fully Programmable Logic Array (PLA) which consists of two independent but interconnected PLA blocks. Each block consists of eight PLA elements, which gives a total of 16 PLA elements. A ...
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Preliminary Technical Data 4-1 Look-up table control 0000 – 0 0001 – NOR 0010 – A AND NOT B 0011 – NOT A 0100 – NOT A AND B 0101 – NOT B 0110 – EXOR 0111 – NAND 1000 ...
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ADuC702x Series 4 PLA IRQ0 enable bit Set by user to enable IRQ0 output from PLA Cleared by user to disable IRQ0 output from PLA 3-0 PLA IRQ0 source 0000 – PLA element 0 0001 – PLA element 1 … ...
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Preliminary Technical Data PROCESSOR REFERENCE PERIPHERALS INTERRUPT SYSTEM There are 24 interrupt sources on the ADuC702x which are controlled by the Interrupt Controller. Most interrupts are generated from the on-chip peripherals like ADC, UART, etc. and two additional interrupt sources ...
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ADuC702x Series registers at the same time. The 32-bit register dedicated to software interrupt is SWICFG described Table 59. This MMR allows the control of Bit Description 31-3 Reserved 2 Programmed Interrupt-FIQ Setting/clearing this bit correspond in setting/clearing bit 1 ...
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Preliminary Technical Data TIMERS The ADuC702x has four general purpose Timer/Counters: - Timer0, - Timer1, - Timer2 or Wake-up Timer, - Timer3 or Watchdog Timer. The four timers in their normal mode of operation can be either free-running or periodic. ...
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ADuC702x Series bit unsigned integers. T1VAL and T1CAP are read-only. - T1CLRI is an 8-bit register. Writing any value to this register will clear the timer1 interrupt. 32kHz Oscillator Core Clock Frequency P0.6 P1.0 Bit Description 31-18 Reserved 17 Event ...
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Preliminary Technical Data The counter can be formatted as plain 32-bit value or as Hours:Minutes:Seconds:Hundreths. Timer 2 can be used to start ADC conversions as shown in the block diagram Figure 30.. Timer2 interface consists in four MMRS: - T2LD ...
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ADuC702x Series value must be written to T3ICLR before the expiration period. This reloads the counter with T3LD and begins a new timeout period. As soon watchdog mode is entered, T3LD and T3CON are write-protected. These two registers can not ...
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Preliminary Technical Data External Memory Interfacing The only ADuC702x models which feature an external memory interface are the ADuC7026 and ADuC7027. The external memory interface requires a larger number of pins, this is why it is only available on larger ...
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ADuC702x Series Cleared by the user to enable one extra clock before and after the Read Strobe Extra bus transition time on Write Set by the user to disable extra bus transition time Cleared by the user to ...
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Preliminary Technical Data MCLK ADDRESS AD 16:0 MSx Figure 34: External Memory Read Cycle MCLK ADDRESS AD 16:0 MSx Figure 35: External Memory Read cycle with Address hold and Bus turn cycles DATA DATA ...
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ADuC702x Series MCLK ADDRESS AD 16:0 MSx Figure 36: External Memory Write Cycle with address and write hold cycles MCLK ADDRESS AD 16:0 MSx Figure 37: External Memory Write Cycle with wait states Preliminary ...
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Preliminary Technical Data ADUC702X HARDWARE DESIGN CONSIDERATIONS POWER SUPPLIES The ADuC702X operational power supply voltage range is 2.7V to 3.6V. Separate analog and digital power supply pins (AV and IOV , respectively) allow noisy digital signals ...
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ADuC702x Series digital and analog sections, as illustrated in Figure 41c. PLACE ANALOG PLACE DIGITAL a. COMPONENTS HERE COMPONENTS HERE AGND PLACE ANALOG PLACE DIGITAL b. COMPONENTS COMPONENTS HERE AGND PLACE ANALOG PLACE DIGITAL c. COMPONENTS COMPONENTS HERE GND Figure ...
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Preliminary Technical Data 3.3V IOV DD 2.5V 1.98V TYP LV DD 128ms TYP POR 0.12ms TYP MRST Figure 44:. ADuC7024/ADuC7025 Internal Power-on-Reset operation TYPICAL SYSEM CONFIGURATION A typical ADuC7024/ADuC7025 configuration is shown in Figure 45. It summarizes some of the ...
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ADuC702x Series DEVELOPMENT TOOLS An entry level, low cost development system is available for the ADuC702X family. This system consists of the following PC- based (Windows® compatible) hardware development tools: Hardware: - ADuC702x Evaluation board - Serial Port programming cable ...
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Preliminary Technical Data OUTLINE DIMENSIONS PIN 1 INDICATOR 12 8MAX 1.00 0.90 0.80 SEATING PLANE Figure 6. 40-Lead Frame Chip Scale Package [LFCSP] (CP-40)—Dimensions shown in millimetres PIN 1 INDICATOR ° MAX ...
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ADuC702x Series Figure 47. 64-Lead LQF Package [LQFP] (S-64)—Dimensions shown in millimetres 0.030 (0.75) 0.020 (0.50) 0.006 (0.15) 0.002 (0.05) Figure 2. 80-Lead LQF Package [LQFP] (S-80)—Dimensions shown in millimetres 0.063 (1.60) MAX 0.47(12.0) 0.006(0.15) 0.002(0.05) 0.39(10.0) BSC 0.024 ± ...