PCA6416A NXP [NXP Semiconductors], PCA6416A Datasheet
PCA6416A
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PCA6416A Summary of contents
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... Input Port register can be inverted with the Polarity Inversion register, saving external logic gates. The system master can reset the PCA6416A in the event of a time-out or other improper operation by asserting a LOW in the RESET input. The power-on reset puts the registers in their default state and initializes the I causes the same reset/initialization to occur without depowering the part ...
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... V (typical) at 2.5 V hys = 0.33 V (typical) at 3.3 V hys = 0.5 V (typical hys 2 C-bus All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 September 2012 PCA6416A 2 C-bus/SMBus I/O expander 2 C-bus. Thus, the PCA6416A can 2 C-bus address 2 C-bus or SMBus. © NXP B.V. 2012. All rights reserved ...
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... ADDR V DD(I2C-bus) V DD(P) RESET Fig 1. PCA6416A Product data sheet Low-voltage translating 16-bit I Description plastic thermal enhanced very very thin quad flat package; no leads; 24 terminals; body 4 4 0.75 mm plastic thin shrink small outline package; 24 leads; body width 4.4 mm plastic very thin fine-pitch ball grid array package; 24 balls; ...
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... Pin configuration for TSSOP24 PCA6416AEV 002aaf786 Transparent top view Pin configuration for VFBGA24 All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 September 2012 PCA6416A 2 C-bus/SMBus I/O expander V DD(P) terminal 1 SDA index area SCL ADDR P0_0 1 P1_7 P0_1 2 P1_6 P0_2 ...
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... Port 1 input/output 7. B5 Address input. Connect directly Serial clock bus. Connect Serial data bus. Connect Supply voltage of PCA6416A for Port P. All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 September 2012 PCA6416A 2 C-bus/SMBus I/O expander or V through a pull-up ...
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... V 7. Functional description Refer to 7.1 Device address The address of the PCA6416A is shown in Fig 6. ADDR is the hardware address package pin and is held to either HIGH (logic 1) or LOW (logic 0) to assign one of the two possible slave addresses. The last bit of the slave address (R/W) defines the operation (read or write performed. A HIGH (logic 1) selects a read operation, while a LOW (logic 0) selects a write operation ...
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... Pointer register and command byte Following the successful acknowledgement of the address byte, the bus master sends a command byte, which is stored in the Pointer register in the PCA6416A. The lower three bits of this data byte state the operation (read or write) and the internal registers (Input, Output, Polarity Inversion, or Configuration) that will be affected ...
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... Output port 0 register (address 02h O0.7 O0.6 O0 Output port 1 register (address 03h O1.7 O1.6 O1 All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 September 2012 PCA6416A 2 C-bus/SMBus I/O expander Section 8. I0.4 I0.3 I0 I1.4 I1.3 I1 Section 8 ...
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... Configuration port 0 register (address 06h C0.7 C0.6 C0 Configuration port 1 register (address 07h C1.7 C1.6 C1 All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 September 2012 PCA6416A 2 C-bus/SMBus I/O expander Section N0.4 N0.3 N0 N1.4 N1.3 N1 Section 8.1 and a register pair ...
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... Fig 8. 7.6 Power-on reset When power (from applied to V PCA6416A in a reset condition until V condition is released and the PCA6416A registers and I initializes to their default states. After that, V back up to the operating voltage for a power-reset cycle. See requirements”. PCA6416A Product data sheet ...
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... Data transfer may be initiated only when the bus is not busy. 8.1 Write commands Data is transmitted to the PCA6416A by sending the device address and setting the Least Significant Bit (LSB logic 0 (see sent after the address and determines which register receives the data that follows the command byte ...
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SCL slave address AD SDA START condition R/W acknowledge from slave write to port data out from port 0 data ...
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... The command byte is sent after the address and determines which register accessed. After a restart, the device address is sent again, but this time the least significant bit is set to a logic 1. Data from the register defined by the command byte is sent by the PCA6416A (see Figure 11 ACK clock pulse ...
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INT t t v(INT) rst(INT) SCL R/W slave address I0.x AD SDA ...
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DATA 00 t h(D) data into port 1 DATA 10 INT t t v(INT) rst(INT) SCL R/W slave address I0.x AD SDA ...
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... The supply current, I DD(P) . DD(P) shows a high value resistor in parallel with the LED. and prevents additional supply current consumption when the LED is DD(P) All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 September 2012 PCA6416A 2 C-bus/SMBus I/O expander V DD(P) 10 kΩ (× DD(P) P0_0 enable ...
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... Fig 15. High value resistor in parallel with 9.2 Power-on reset requirements In the event of a glitch or data corruption, PCA6416A can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application ...
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... Figure 19 DD(P) ∆V DD(gl) t w(gl)VDD POR and Table 15 provide more details on this specification. V DD(P) ) DD(P) ) DD(P) POR POR All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 September 2012 PCA6416A 2 C-bus/SMBus I/O expander Min 0.1 0 [1] - [ DD(P) ) are dependent on each DD(gl) and Table 15 ...
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... DD(I2C-bus) Conditions SCL, SDA, RESET ADDR, P1_7 to P0_0 SCL, SDA, RESET ADDR, P1_7 to P0_0 P1_7 to P0_0 P1_7 to P0_0 operating in free air All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 September 2012 PCA6416A 2 C-bus/SMBus I/O expander Min Max 0.5 +6.5 0.5 +6.5 0.5 [1] +6.5 ...
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... DD DD DD DD DD DD(P) All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 September 2012 PCA6416A 2 C-bus/SMBus I/O expander Max Unit [1] 88 K/W [1] 66 K/W [1] 171 K/W [1] Min Typ Max Unit 1 1.1 1.4 V [2] 1 [2] 1 ...
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... I/O DD(I2C-bus I/O DD(P) SS DD( C. = 3.3 V and T amb = 0.4 V and V = 3.3 V. Typical value for All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 September 2012 PCA6416A 2 C-bus/SMBus I/O expander Min DD(I2C-bus 1. 5 DD(I2C-bus DD(P) = 400 kHz - - - ...
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... DD(P) 1. (°C) amb Fig 22. Standby supply current versus (μ 1.5 2.5 3.5 All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 September 2012 PCA6416A 2 C-bus/SMBus I/O expander 1400 V = 5.5 V DD(P) 5.0 V 1000 3.6 V 3.3 V 800 600 400 2.5 V 2.3 V 200 1 −40 − ...
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... V ( 002aaf580 I sink (mA) 0.2 0 002aaf582 I sink (mA) 0.2 0.3 V (V) OL All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 September 2012 PCA6416A 2 C-bus/SMBus I/O expander −40 °C amb 25 ° ° 0.1 0.2 = 1.8 V DD( −40 °C amb 25 °C 85 ° ...
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... 002aaf563 I source (mA) 0.4 0.6 V − V (V) DD( 002aaf565 I source (mA) 0.4 0.6 V − V (V) DD(P) OH All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 September 2012 PCA6416A 2 C-bus/SMBus I/O expander −40 °C 30 amb 25 °C 85 ° 0.2 0.4 V DD(P) = 1.8 V DD( −40 °C 60 amb 25 ° ...
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... Fig 26. LOW-level output voltage versus temperature PCA6416A Product data sheet Low-voltage translating 16-bit I 002aah056 V DD( (°C) amb Fig 27. I/O high voltage versus temperature All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 September 2012 PCA6416A 2 C-bus/SMBus I/O expander 200 − V (mV) OH 160 120 V = 1.8 V DD( − ...
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... Product data sheet Low-voltage translating 16-bit I Conditions SCL LOW to SDA output valid ACK signal from SCL LOW to SDA (out) LOW Conditions [1] All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 September 2012 PCA6416A 2 C-bus/SMBus I/O expander Figure 29. 2 Standard-mode Fast-mode C-bus Min ...
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... Input port register R/W Address Bit 0 Bit 1 (LSB HIGH SP t VD;DAT SU;DAT HD;DAT All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 September 2012 PCA6416A 2 C-bus/SMBus I/O expander Standard-mode 2 I C-bus Min Max - 400 0 - 300 - kΩ ...
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... DATA 1 0.5 × V SCL R/W DD(I2C-bus) 0.5 × V INT DD(P) All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 September 2012 PCA6416A 2 C-bus/SMBus I/O expander 4.7 kΩ 100 pF 002aag979 acknowledge no acknowledge from slave from master data from port A DATA rst(INT) ...
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... v(Q) last stable bit unstable data h(D) su(D) on SCL I/O (Pn) output. DD(I2C-bus) All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 September 2012 PCA6416A 2 C-bus/SMBus I/O expander 500 Ω 2 × V DD(P) 002aag981 0.7 × V DD(I2C-bus) P7 0.3 × V DD(I2C-bus) 002aag982 0.7 × V DD(I2C-bus) P7 0.3 × V DD(I2C-bus) 0.5 × ...
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... Fig 31. Reset load circuits and voltage waveforms PCA6416A Product data sheet Low-voltage translating 16-bit kΩ 002aag977 All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 September 2012 PCA6416A 2 C-bus/SMBus I/O expander 500 Ω Pn DUT 500 Ω port load configuration ...
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... 2.5 scale (1) ( 4.1 2.25 4.1 2.25 0.5 2.5 3.9 1.95 3.9 1.95 REFERENCES JEDEC JEITA - - - MO-220 All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 September 2012 PCA6416A 2 C-bus/SMBus I/O expander detail 0.5 2.5 0.1 0.05 0.05 0.1 0.3 EUROPEAN PROJECTION SOT994-1 c ISSUE DATE ...
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... 2.5 scale (1) ( 0.30 0.2 7.9 4.5 0.65 0.19 0.1 7.7 4.3 REFERENCES JEDEC JEITA MO-153 All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 September 2012 PCA6416A 2 C-bus/SMBus I/O expander detail 6.6 0.75 0.4 1 0.2 0.13 6 ...
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... 3.1 3.1 3.0 3.0 0 0.15 0.05 2.9 2.9 References JEDEC JEITA - - - All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 September 2012 PCA6416A 2 C-bus/SMBus I/O expander detail 0.08 0.1 European projection SOT1199-1 sot1199-1_po Issue date 11-02-16 12-03-13 © NXP B.V. 2012. All rights reserved. ...
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... Solder bath specifications, including temperature and impurities PCA6416A Product data sheet Low-voltage translating 16-bit I All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 September 2012 PCA6416A 2 C-bus/SMBus I/O expander © NXP B.V. 2012. All rights reserved ...
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... Package reflow temperature (C) 3 Volume (mm ) < 350 260 260 250 Figure 35. All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 September 2012 PCA6416A 2 C-bus/SMBus I/O expander Figure 35) than a SnPb process, thus 350 220 220 350 to 2000 > 2000 260 260 250 ...
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... MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature MSL: Moisture Sensitivity Level All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 September 2012 PCA6416A 2 C-bus/SMBus I/O expander peak temperature time 001aac844 © NXP B.V. 2012. All rights reserved. ...
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... Refer to the package outline drawing for actual layout 0.400 0.600 8.200 5.300 8.600 All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 September 2012 PCA6416A 2 C-bus/SMBus I/O expander (0.125) (0.125 7.450 © NXP B.V. 2012. All rights reserved. SOT355-1 sot355-1_fr ...
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... Refer to the package outline drawing for actual layout C D SLx SLy SPx tot 0.900 0.240 2.100 2.100 1.200 All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 September 2012 PCA6416A 2 C-bus/SMBus I/O expander 0.025 0.025 SPx SPy SLy By SPy tot SPx SPy ...
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... LED LSB MSB NACK PCB POR PRR SMBus 20. Revision history Table 26. Revision history Document ID Release date PCA6416A v.1 20120911 PCA6416A Product data sheet Low-voltage translating 16-bit I Abbreviations Description ElectroStatic Discharge Field-Effect Transistor General Purpose Input/Output Inter-Integrated Circuit bus Input/Output Light-Emitting Diode Least Significant Bit ...
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... All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 September 2012 PCA6416A 2 C-bus/SMBus I/O expander © NXP B.V. 2012. All rights reserved ...
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... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 September 2012 PCA6416A 2 C-bus/SMBus I/O expander © NXP B.V. 2012. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCA6416A 2 C-bus/SMBus I/O expander All rights reserved. Date of release: 11 September 2012 Document identifier: PCA6416A ...