PTN3700EV NXP [NXP Semiconductors], PTN3700EV Datasheet
PTN3700EV
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PTN3700EV Summary of contents
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PTN3700 1.8 V simple mobile interface link bridge IC Rev. 2 — 8 June 2011 1. General description The PTN3700 is a 1.8 V simple mobile interface link bridge IC which can function both as a transmitter-serializer or a receiver-deserializer ...
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NXP Semiconductors The PTN3700 automatically rotates the order of the essential signals (parallel CMOS and high-speed serial data and clock) depending on whether it is operating as transmitter or as receiver (using pin TX/RX). In addition, two Pinning Select bits ...
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... Type number Solder process PTN3700EV/G Pb-free (SnAgCu solder ball compound) [1] 0.5 mm ball pitch; 1.0 mm maximum package height. 4.1 Ordering options Table 2. Type number PTN3700EV/G 5. Functional diagram PSEL[1:0] Fig 1. PTN3700 Product data sheet Package Name Description VFBGA56 plastic very thin fine-pitch ball grid array package; ...
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NXP Semiconductors D0+ D0− D1+ D1− D2+ D2− CLK+ CLK− FM FSS F/XS XSD LS[1:0] PSEL[1:0] Fig 2. PTN3700 Product data sheet PTN3700 DESERIALIZER N × PCLK PLL DDR → SDR 2 2 TX/RX = LOW Functional diagram of PTN3700 ...
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... D2− XSD D2+ CPO R7 R5 56-ball, 7 8 grid; transparent top view Fig 6. VFBGA56 ball mapping - Transmitter mode (TX/RX = HIGH); PSEL[1:0] = 10b PTN3700 Product data sheet ball A1 PTN3700EV/G index area 002aac377 Transparent top view ...
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NXP Semiconductors D2+ VDDA D2− GNDA D1+ TX/RX A1 GND D D1− VDD PSEL0 LS0 E CLK+ GND PSEL1 LS1 F CLK− F/XS A0 GND G D0+ XSD VS ...
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NXP Semiconductors 6.2 Pin description Table 3. Pin description - Transmitter mode [1] Symbol Pin Type Parallel data inputs R[7:0], G[7:0], B[7:0] CMOS HS CMOS VS CMOS DE CMOS A0, A1 CMOS High-speed serial outputs D0+, D0, D1+, D1, SubLVDS ...
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NXP Semiconductors Table 4. Pin description - Receiver mode [1] Symbol Pin Type Parallel data outputs R[7:0], G[7:0], B[7:0] CMOS HS CMOS VS CMOS DE CMOS A0, A1 CMOS High-speed serial inputs D0+, D0, D1+, SubLVDS D1, D2+, D2 receiver ...
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NXP Semiconductors 7. Functional description 7.1 General A complete simple mobile interface link consists of one PTN3700 configured as transmitter (see channels; and one PTN3700 configured as receiver (see ground are supplied to pins VDD and GND respectively (power and ...
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NXP Semiconductors 7.2 Link programmability The number of high-speed serial channels used is programmed by CMOS input pins LS[1:0]. For a given link consisting of a transmitter and receiver pair of PTN3700’s, the number of channels used must be programmed ...
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... [1] For PTN3700EV/G VFBGA56 package option. See also PTN3700 Product data sheet Versatile signal mirroring programmability - Parallel I/O [ (Receive mode PCLK ...
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... [1] For PTN3700EV/G VFBGA56 package option. See also 7.4 High-speed data channel protocol options The PTN3700 maps the transmission protocol in accordance with the serialization mode selected by pins LS[1:0]. In Mode 00 (1-channel), all RGB, parity and synchronization bits are serialized onto a single 30-bit sequence. In Mode 01 (2-channel), these bits are mapped onto two simultaneous 15-bit sequences divided across two lanes ...
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NXP Semiconductors 7.4.1 Serial protocol bit mapping - pseudo source synchronous mode (FSS = LOW (differential) CLK (differential) Fig 12. Mode 00 - single serial data channel mode (FSS = LOW (differential ...
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NXP Semiconductors 7.4.2 Serial protocol bit mapping - fully source synchronous mode (FSS = HIGH (differential) CLK (differential) Fig 15. Mode 00 - single serial data channel mode (FSS = HIGH) (differential) (differential) (differential) Fig 16. ...
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NXP Semiconductors 7.4.3 PLL, PCLK, CLK and pixel synchronization 7.4.3.1 Pixel synchronization PSS mode: synchronization. At the receiver side, a PLL is needed to re-generate the bit clock, translating to a higher receiver power dissipation. FSS mode: synchronization words are ...
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NXP Semiconductors Table 8. FSS LOW HIGH [1] ‘X’ signifies that PTN3700 handles this signal transparently, i.e., data is transmitted and received as-is. [2] ‘R, G, B’ signifies that video data have to be input according to ...
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NXP Semiconductors Fig 18. Typical video screen 7.5 Power modes The PTN3700 has three different power modes to minimize power consumption of the link as a function of link activity: Shutdown mode, Standby mode, and Active mode. The truth table ...
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NXP Semiconductors Table 10. Inputs XSD CLK+, CLK floating H stopped H running 7.6 Link error detection and correction In Transmitter mode, PTN3700 calculates an odd parity bit and merges this into the serialized output data stream ...
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NXP Semiconductors Table 12. Parity decoding function table - Receiver mode Inputs of bits received in frame = H XSD Clock (R[7:0], G[7:0], B[7:0], HS, VS, DE) H running H running H running H running H stopped L X ...
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NXP Semiconductors 7.8 Auxiliary signals The two auxiliary bits A[1:0] are user-supplied bits that can be additionally serialized and deserialized by the PTN3700 in transmitter and receiver modes, respectively. These auxiliary bits are transparent to the PTN3700 and can be ...
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NXP Semiconductors 10. Static characteristics Table 16. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter V supply voltage DD V HIGH-level input voltage IH V LOW-level input voltage IL V ...
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NXP Semiconductors Table 16. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter Receiver mode, PSS mode (TX/RX = LOW; FSS = LOW) I supply current DD Receiver mode, FSS mode ...
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NXP Semiconductors 11. Dynamic characteristics 11.1 Transmitter mode Table 17. Dynamic characteristics for Transmitter mode 1. 1. amb All CMOS input signals’ rise time and fall time to Transmitter are ...
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NXP Semiconductors 11.2 Receiver mode Table 18. Dynamic characteristics for Receiver mode 1. 1. amb CMOS output load pF. L Symbol Parameter f output frequency on o(PCLK) ...
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NXP Semiconductors Fig 20. AC timing diagram - Receiver mode PTN3700 Product data sheet 1.8 V simple mobile interface link bridge IC VS, HS, DE, R[7:0], G[7:0], B[7:0] t sk(Q) PCLK All information provided in this document is subject to ...
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NXP Semiconductors 11.3 Power-on/power-off sequence 11.3.1 Power-on sequence Table 19. Power-on sequence timing characteristics 1. 1. amb These values are for transitions of the Shutdown mode to the Standby mode ...
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NXP Semiconductors 11.3.2 Power-off sequence Table 20. Power-off sequence timing characteristics 1. 1. amb These values are for transition of the Active mode to the Standby mode. Symbol Parameter t ...
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NXP Semiconductors 11.4 High-speed signaling channel Table 21. High-speed signaling channel SubLVDS output characteristics, Transmitter mode 1. 1. amb Symbol Parameter V differential output O(dif) voltage V common-mode output O(cm) ...
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NXP Semiconductors Table 22. High-speed signaling channel SubLVDS input characteristics, Receiver mode 1. 1. amb Symbol Parameter V differential input voltage I(dif) V differential input HIGH-level th(H)i(dif) threshold voltage V ...
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NXP Semiconductors 12. Application information 12.1 Typical lane and PCLK configurations The PTN3700 supports PCLK (pixel clock) frequencies from 4 MHz to 65 MHz over data lanes. overhead Note that 20 % overhead ...
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NXP Semiconductors VDD GND FSS LS1 LS0 ...
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NXP Semiconductors 12.3 Power decoupling configuration The PTN3700 needs 1 regulator, and use a 10 resistor for isolation. The recommended power configuration of the decoupling is shown in capacitor for each VDD pin and one 0.01 F ...
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NXP Semiconductors It is recommended to have long enough of a power-off time to let V completely, reaching to ground level. If the supply voltage V recommended to hold the XSD pin at LOW during power-on. Fig 27. XSD at ...
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NXP Semiconductors Fig 30. Voltage waveforms, differential input or output voltage and rise and fall time Fig 31. Receiver measurement definition for measurement of electrical parameters Fig 32. Voltage waveforms, input threshold voltage measurements Fig 33. Transmitter high-speed serial outputs ...
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NXP Semiconductors Fig 34. Receiver high-speed serial inputs timing relationships (PSS mode) Fig 35. Transmitter and receiver high-speed serial outputs and inputs timing PTN3700 Product data sheet CLK (differential) t bit N bit(CLKH-D) t bit 1 bit(CLKH-D) t bit 0 ...
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NXP Semiconductors 14. Package outline VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4 x 4.5 x 0.65 mm ball A1 index area ball A1 index area DIMENSIONS ...
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NXP Semiconductors 15. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 15.1 Introduction to ...
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NXP Semiconductors 15.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including ...
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NXP Semiconductors Fig 37. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 16. Abbreviations Table 26. Acronym CIF CMOS DDR EMI fps HVGA I/O LVDS ...
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NXP Semiconductors Table 26. Acronym WVGA XGA XVGA 17. Revision history Table 27. Revision history Document ID Release date PTN3700 v.2 20110608 • Modifications: Added • Updated soldering information PTN3700 v.1 20070814 PTN3700 Product data sheet Abbreviations …continued Description Wide ...
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NXP Semiconductors 18. Legal information 18.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...
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NXP Semiconductors Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use neither qualified nor tested in accordance with automotive testing ...
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NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . ...