DS8908BN NSC [National Semiconductor], DS8908BN Datasheet - Page 6

• Manufacturer Part Number: DS8908BN
• Description: DS8908B AM/FM Digital Phase-Locked Loop Frequency Synthesizer
• Manufacturer: NSC [National Semiconductor]

will not be changed when ENABLE returns high
accepted as data and are shifted successively into the in-
Timing Diagrams
SERIAL DATA ENTRY INTO THE DS8908B
Serial information entry into the DS8908B is enabled by a
low level on the ENABLE input One binary bit is then ac-
cepted from the DATA input with each positive transition of
the CLOCK input The CLOCK input must be low for the
specified time preceding and following the negative tran-
sition of the ENABLE input
The first two bits accepted following the negative transition
of the ENABLE input are interpreted as address If these
address bits are not 1 1 no further information will be ac-
cepted fromt he DATA inputs and the internal data latches
If these first two bits are 1 1 then all succeeding bits are
ternal shift register as long as ENABLE remains low
Any data bits preceding the 19th to last bit will be shifted
out and thus are irrelevant Data bits are counted as any
bits following two valid address bits (1 1) with the ENABLE
low When the ENABLE input returns high any further serial
data entry is inhibited Upon this positive transition the data
in the internal shift register is transferred into the internal
data latches Note that until this time the states of the inter-
nal data latches have remained unchanged
Truth Table
Timing diagrams are not drawn to scale Scale within any one drawing may not be consistent and intervals are defined positive as drawn
(Continued)
Bit 16
AM FM Frequency Synthesizer (Scan Mode)
Reference Frequency Selection Truth Table
1
1
0
0
Serial Data
Bit 17
1
0
1
0
6
These data bits are interpreted as follows
Data Bit Position
Last
2nd to Last
3rd to Last
4th to Last
5th to Last
6th to Last
7th to Last
8th to Last
9th to Last
10th to Last
11th to Last
12th to Last
13th to Last
14th to Last
15th to Last
16th to Last
17th to Last
18th to Last
19th to Last
Note 1 See Reference Frequency Select Truth Table
Note 2 The actual divide code is N
Frequency
Reference
(kHz)
20
10
9
1
Bit 19 Output (Pin 2)
Bit 18 Output (Pin 1)
Ref Freq Select Bit
Ref Freq Select Bit
AM FM Select Bit 15
LSB of
a
1 ie the number loaded plus 1
Data Interpretation
d
N(2
(2
(2
(2
(2
(2
(2
(2
(2
(2
(2
(2
(2
(2
13
12
11
10
9
8
7
6
5
4
3
2
1
0
)
)
)
)
)
)
)
)
)
)
)
)
)
)
(1)
(1)
d
TL F 5111– 12
17
16
N
(2)