AT89S51-24 ATMEL [ATMEL Corporation], AT89S51-24 Datasheet

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AT89S51-24

Manufacturer Part Number
AT89S51-24
Description
8-bit Microcontroller with 4K Bytes In-System Programmable Flash
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet

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Features
Description
The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K
bytes of in-system programmable Flash memory. The device is manufactured using
Atmel’s high-density nonvolatile memory technology and is compatible with the indus-
try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program
memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-
grammer. By combining a versatile 8-bit CPU with in-system programmable Flash on a
monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a
highly-flexible and cost-effective solution to many embedded control applications.
The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes of
RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five-
vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and
clock circuitry. In addition, the AT89S51 is designed with static logic for operation
down to zero frequency and supports two software selectable power saving modes.
The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and
interrupt system to continue functioning. The Power-down mode saves the RAM con-
tents but freezes the oscillator, disabling all other chip functions until the next external
interrupt or hardware reset.
Compatible with MCS-51
4K Bytes of In-System Programmable (ISP) Flash Memory
4.0V to 5.5V Operating Range
Fully Static Operation: 0 Hz to 33 MHz
Three-level Program Memory Lock
128 x 8-bit Internal RAM
32 Programmable I/O Lines
Two 16-bit Timer/Counters
Six Interrupt Sources
Full Duplex UART Serial Channel
Low-power Idle and Power-down Modes
Interrupt Recovery from Power-down Mode
Watchdog Timer
Dual Data Pointer
Power-off Flag
Fast Programming Time
Flexible ISP Programming (Byte and Page Mode)
– Endurance: 1000 Write/Erase Cycles
®
Products
8-bit
Microcontroller
with 4K Bytes
In-System
Programmable
Flash
AT89S51
Rev. 2487A–10/01
1

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AT89S51-24 Summary of contents

Page 1

... Atmel AT89S51 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications. The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five- vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry ...

Page 2

... XTAL1 19 22 GND 20 21 TQFP (MOSI) P1.5 1 (MISO) P1.6 2 (SCK) P1.7 3 RST 4 (RXD) P3 (TXD) P3.1 7 (INT0) P3.2 8 (INT1) P3.3 9 (T0) P3.4 10 (T1) P3.5 11 AT89S51 2 VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11) P2.2 (A10) P2.1 (A9) P2.0 (A8) 33 P0.4 (AD4) 32 P0.5 (AD5) 31 P0.6 (AD6) 30 P0.7 (AD7) 29 ...

Page 3

... RAM LATCH ACC TMP2 TMP1 ALU INTERRUPT, SERIAL PORT, AND TIMER BLOCKS PSW PORT 3 LATCH PORT 3 DRIVERS P3.0 - P3.7 P2.0 - P2.7 PORT 2 DRIVERS FLASH LATCH PROGRAM STACK ADDRESS POINTER REGISTER BUFFER PC INCREMENTER PROGRAM COUNTER DUAL DPTR PROGRAM PORT 1 ISP LOGIC LATCH PORT PORT 1 DRIVERS P1.0 - P1.7 AT89S51 3 ...

Page 4

... As inputs, Port 3 pins that are externally being pulled low will source current (I Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S51, as shown in the following table. AT89S51 4 ) because of the internal pull-ups ...

Page 5

... PSEN Program Store Enable (PSEN) is the read strobe to external program memory. When the AT89S51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA/VPP External Access Enable ...

Page 6

... Note that not all of the addresses are occupied, and unoccupied addresses may not be imple- Registers mented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. Table 1. AT89S51 SFR Map and Reset Values 0F8H B 0F0H ...

Page 7

... ALE is active only during a MOVX or MOVC instruction Disable/Enable Reset out DISRTO 0 Reset pin is driven High after WDT times out 1 Reset pin is input only Disable/Enable WDT in IDLE mode WDT continues to count in IDLE mode WDT halts counting in IDLE mode AT89S51 Reset Value = XXX00XX0B DISRTO – – DISALE ...

Page 8

... FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to external memory. Data Memory The AT89S51 implements 128 bytes of on-chip RAM. The 128 bytes are accessible via direct and indirect addressing modes. Stack operations are examples of indirect addressing, so the 128 bytes of data RAM are available as stack space. ...

Page 9

... Overview’. Timer 0 and 1 Timer 0 and Timer 1 in the AT89S51 operate the same way as Timer 0 and Timer 1 in the AT89C51. For further information on the timers’ operation, refer to the ATMEL Web site (http://www.atmel.com). From the home page, select ‘Products’, then ‘8051-Architecture Flash Microcontroller’ ...

Page 10

... Enable Bit = 1 enables the interrupt. Enable Bit = 0 disables the interrupt. Symbol EA – – ES ET1 EX1 ET0 EX0 User software should never write 1s to reserved bits, because they may be used in future AT89 products. Figure 1. Interrupt Sources AT89S51 10 EA – – ES Position IE.7 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0 ...

Page 11

... V enough to allow the oscillator to restart and stabilize. 2487A–10/ C1 for Crystals = for Ceramic Resonators NC EXTERNAL OSCILLATOR SIGNAL is restored to its normal operating level and must be held active long CC AT89S51 XTAL2 XTAL1 GND XTAL2 XTAL1 GND 11 ...

Page 12

... Table 5. Status of External Pins During Idle and Power-down Modes Mode Idle Idle Power-down Power-down Program The AT89S51 has three lock bits that can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the following table. Memory Lock Bits Table 6. Lock Bit Protection Modes 1 2 ...

Page 13

... XTAL1 and XTAL2. The maximum serial clock (SCK) frequency should be less than 1/16 of the crystal frequency. With a 33 MHz oscillator clock, the maximum SCK fre- quency is 2 MHz. Serial To program and verify the AT89S51 in the serial programming mode, the following sequence is recommended: Programming Algorithm 1 ...

Page 14

... Notes: 1. Each PROG pulse is 200 ns - 500 ns for Chip Erase. 2. Each PROG pulse is 200 ns - 500 ns for Write Code Data. 3. Each PROG pulse is 200 ns - 500 ns for Write Lock Bits. 4. RDY/BSY signal is output on P3.0 during programming don’t care. AT89S51 14 power off. CC ALE/ EA/ ...

Page 15

... XTAL1 RST GND PSEN AT89S51 ADDR. P1.0-P1.7 CC 0000H/FFFH P0 P2 A11 P2.6 P2.7 ALE SEE FLASH P3.3 PROGRAMMING MODES TABLE P3.6 P3.7 XTAL 2 EA 3-33 MHz XTAL1 RST GND PSEN AT89S51 V CC PGM DATA PROG RDY/ BSY PGM DATA (USE 10K PULLUPS ...

Page 16

... Data Float After ENABLE EHQZ t PROG High to BUSY Low GHBL t Byte Write Cycle Time WC Figure 6. Flash Programming and Verification Waveforms – Parallel Mode P1.0 - P1.7 P2.0 - P2.3 PORT 0 ALE/PROG EA/V PP P2.7 (ENABLE) P3.0 (RDY/BSY) AT89S51 16 PP PROGRAMMING ADDRESS DATA DVGL GHDX t t AVGL GHAX t t SHGL GHSL t ...

Page 17

... Figure 7. Flash Memory Serial Downloading Flash Programming and Verification Waveforms – Serial Mode Figure 8. Serial Programming Waveforms 2487A–10/01 AT89S51 INSTRUCTION P1.5/MOSI INPUT P1.6/MISO DATA OUTPUT P1.7/SCK CLOCK IN XTAL2 3-33 MHz XTAL1 GND AT89S51 RST ...

Page 18

... For Page Read/Write, the data always starts from byte 0 to 255. After the command byte and upper address byte are latched, each byte thereafter is treated as data until all 256 bytes are shifted in/out. Then the next instruction will be ready to be decoded. AT89S51 18 Byte 2 ...

Page 19

... MOSI t t OVSH SCK t SHSL MISO = - Min CLCL 8 t CLCL t CLCL 2 t CLCL 10 t SLSH SHOX t SLIV = 4.0 - 5.5V (Unless Otherwise Noted) CC Typ Max 500 400 CLCL AT89S51 Units MHz µs 19 ...

Page 20

... Port Ports Maximum total I for all output pins exceeds the test condition than the listed test conditions. 2. Minimum V for Power-down is 2V. CC AT89S51 20 *NOTICE: = -40°C to 85°C and Condition (Except EA) (Except XTAL1, RST) (XTAL1, RST) (Ports ...

Page 21

... CLCL 203 4t -75 CLCL 23 t -30 CLCL 433 7t -130 CLCL 33 t -25 CLCL 0 43 123 t -25 CLCL AT89S51 Max Units 33 MHz -65 ns CLCL -60 ns CLCL ns t -25 ns CLCL ns 5t -80 ns CLCL ...

Page 22

... External Program Memory Read Cycle ALE PSEN PORT 0 PORT 2 External Data Memory Read Cycle ALE PSEN RD PORT FROM RI OR DPL PORT 2 AT89S51 22 t LHLL t t AVLL LLIV t LLPL t PLIV t PLAZ t LLAX t PXIX INSTR IN t AVIV A8 - A15 t LHLL t LLDV t RLRH ...

Page 23

... QVWX AVLL t QVWH FROM RI OR DPL DATA OUT t AVWL P2 A15 FROM DPH t t CHCX CLCH CLCX Min AT89S51 t WHLH t WHQX FROM PCL INSTR A15 FROM PCH t CHCX t CHCL t CLCL Max Units 33 MHz ...

Page 24

... IL (1) Float Waveforms Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded V AT89S51 24 = 4.0V to 5.5V and Load Capacitance = 80 pF MHz Osc Min 1.0 ...

Page 25

... Ordering Information Speed Power (MHz) Supply Ordering Code 24 4.0V to 5.5V AT89S51-24AC AT89S51-24JC AT89S51-24PC AT89S51-24AI AT89S51-24JI AT89S51-24PI 33 4.5V to 5.5V AT89S51-33AC AT89S51-33JC AT89S51-33PC = Preliminary Availability 44A 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44-lead, Plastic J-leaded Chip Carrier (PLCC) 40P6 40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP) 2487A– ...

Page 26

... MAX SEATING PLANE .161(4.09) .125(3.18) .065(1.65) .110(2.79) .041(1.04) .090(2.29) .630(16.0) .590(15.0) .012(.305) .008(.203) .690(17.5) .610(15.5) AT89S51 26 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) 12.21(0.478) SQ 11.75(0.458) 0.45(0.018) .032(.813) 0.30(0.012) .026(.660) .050(1.27) TYP 10.10(0.394) SQ 9.90(0.386) 1 ...

Page 27

Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Atmel Asia, Ltd. ...

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