ISL6535 INTERSIL [Intersil Corporation], ISL6535 Datasheet - Page 9

• Manufacturer Part Number: ISL6535
• Description: Synchronous Buck Pulse-Width Modulator PWM Controller
• Manufacturer: INTERSIL [Intersil Corporation]

Locate the ISL6535 within 2 to 3 inches of the MOSFETs, Q
and Q
circuit traces for the MOSFETs’ gate and source connections
from the ISL6535 must be sized to handle up to 3A peak
current. Minimize any leakage current paths on the SS pin
and locate the capacitor C
internal current source is only 30µA. Provide local V
decoupling between VCC and GND pins. Locate the
capacitor C
the phase node.
FIGURE 7. VOLTAGE-MODE BUCK CONVERTER
FIGURE 6. COMPENSATION CONFIGURATION FOR THE
CIRCUIT
PWM
2
(1 inch or less for 500kHz or higher operation). The
C
R
3
3
COMP
BOOT
COMPENSATION DESIGN
ISL6535 CIRCUIT
HALF-BRIDGE
OSCILLATOR
V
as close as practical to the BOOT pin and
OSC
E/A
DRIVE
R
R
R
1
ISL6535
2
2
VOUT
C
+
-
VREF
C
2
ss
2
C
C
close to the SS pin as the
1
9
1
FB
PHASE
UGATE
LGATE
EXTERNAL CIRCUIT
GND
COMP
R
FB
3
V
IN
R
1
C
L
3
ISL6535
DCR
V
ESR
OUT
C
CC
1
ISL6535
Compensating the Converter
The ISL6535 Single-phase converter is a voltage-mode
controller. This section highlights the design consideration for a
voltage-mode controller requiring external compensation. To
address a broad range of applications, a type-3 feedback
network is recommended (see Figure 6).
Figure 7 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage is
regulated to the reference voltage level. The error amplifier
output is compared with the oscillator triangle wave to
provide a pulse-width modulated wave with an amplitude of
V
output filter. The output filter capacitor bank’s equivalent
series resistance is represented by the series resistor ESR.
The modulator transfer function is the small-signal transfer
function of V
DC gain and shaped by the output filter, with a double pole
break frequency at F
of this analysis, L and DCR represent the output inductance
and its DCR, while C and ESR represents the total output
capacitance and its equivalent series resistance.
The compensation network consists of the error amplifier
(internal to the ISL6535) and the external R
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F
margin (better than 45°). Phase margin is the difference
between the closed loop phase at F
equations that follow relate the compensation network’s poles,
zeros and gain to the components (R
C
locating the poles and zeros of the compensation network:
F
1. Select a value for R
2. Calculate C
IN
3
LC
) in Figures 6 and 7. Use the following guidelines for
value for R
setting the output voltage to be equal to the reference set
voltage, as shown in Figure 7, the design procedure can
be followed as presented.
As the ISL6535 supports 100% duty cycle, D
The ISL6535 uses a fixed ramp amplitude (V
Equation 8 simplifies to Equation 9:
at 0.1 to 0.75 of F
Equation 10 to the desired number). The higher the quality
factor of the output filter and/or the higher the ratio F
the lower the F
F
at the PHASE node. The PWM wave is smoothed by the
R
R
=
LC
2
2
---------------------------
2π
=
=
).
--------------------------------------------- -
D
1.9 R
------------------------------ -
⋅
V
V
MAX
1
OSC
IN
0
L C
OUT
⋅
; typically 0.1 to 0.3 of f
⋅
⋅
2
1
1
F
⋅
such that F
for desired converter bandwidth (F
⋅
V
LC
/V
⋅
R
F
IN
Z1
COMP
1
0
⋅
LC
⋅
LC
frequency (to maximize phase boost at
F
F
LC
0
1
(to adjust, change the 0.5 factor in
and a zero at F
. This function is dominated by a
F
(1kΩ to 10kΩ, typically). Calculate
CE
Z1
is placed at a fraction of the F
=
-------------------------------- -
2π C ESR
⋅
0dB
SW
1
1
, R
⋅
) and adequate phase
and 180°. The
CE
2
, R
. For the purpose
1
to R
3
, C
MAX
OSC
3
1
, C
, C
0
equals 1.
) of 1.9V,
May 5, 2008
1
). If
CE
2
(EQ. 8)
(EQ. 9)
(EQ. 7)
FN9255.1
to C
, and
/F
LC
LC
3
,
,