MC68HC908LJ12CPB FREESCALE [Freescale Semiconductor, Inc], MC68HC908LJ12CPB Datasheet - Page 125

• Manufacturer Part Number: MC68HC908LJ12CPB
• Description: 8-bit microcontroller units
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Clock Generator Module (CGM)
8.8.2 Stop Mode
8.8.3 CGM During Break Interrupts
Technical Data
126
If the oscillator stop mode enable bit (STOP_XCLKEN in CONFIG2
register) is configured to disabled the oscillator in stop mode, then the
STOP instruction disables the CGM (oscillator and phase locked loop)
and holds low all CGM outputs (CGMOUT, CGMVCLK, CGMPCLK, and
CGMINT).
If the STOP instruction is executed with the divided VCO clock,
CGMPCLK, divided by two driving CGMOUT, the PLL automatically
clears the BCS bit in the PLL control register (PCTL), thereby selecting
the oscillator clock, CGMXCLK, divided by two as the source of
CGMOUT. When the MCU recovers from STOP, the crystal clock
divided by two drives CGMOUT and BCS remains clear.
If the oscillator stop mode enable bit is configured for continuous
oscillator operation in stop mode, then the phase locked loop is shut off
but the CGMXCLK will continue to drive the SIM and other MCU sub-
systems.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See
Register.)
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect the PLLF bit during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
the PLL control register during the break state without affecting the PLLF
bit.
Clock Generator Module (CGM)
9.8.3 SIM Break Flag Control
MC68HC908LJ12
Freescale Semiconductor
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Rev. 2.1