MPC8572CLPXARLD FREESCALE [Freescale Semiconductor, Inc], MPC8572CLPXARLD Datasheet - Page 81

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MPC8572CLPXARLD

Manufacturer Part Number
MPC8572CLPXARLD
Description
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
The other detailed AC requirements of the SerDes Reference Clocks is defined by each interface protocol
based on application usage. Refer to the following sections for detailed information:
15.2.4.1
SD1_REF_CLK/SD1_REF_CLK are designed to work with a spread spectrum clock (+0 to –0.5%
spreading at 30–33 KHz rate is allowed), assuming both ends have same reference clock. For better results,
a source without significant unintended modulation should be used.
SD2_REF_CLK/SD2_REF_CLK are not to be used with, and should not be clocked by, a spread spectrum
clock source.
15.3
Figure 54
The DC and AC specification of SerDes data lanes are defined in each interface protocol section below
(PCI Express, Serial Rapid IO or SGMII) in this document based on the application usage:
Freescale Semiconductor
Section 8.3.2, “AC Requirements for SGMII SD2_REF_CLK and SD2_REF_CLK”
Section 16.2, “AC Requirements for PCI Express SerDes Reference
Section 17.2, “AC Requirements for Serial RapidIO SD1_REF_CLK and SD1_REF_CLK”
Section 8.3, “SGMII Interface Electrical
SerDes Transmitter and Receiver Reference Circuits
shows the reference circuits for SerDes data lane’s transmitter and receiver.
SD n _REF_CLK
SD n _REF_CLK
Spread Spectrum Clock
Figure 53. Single-Ended Measurement Points for Rise and Fall Time Matching
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Transmitter
Figure 54. SerDes Transmitter and Receiver Reference Circuits
50 Ω
50 Ω
SD1_TX n or
SD2_TX n
SD1_TX n or
SD2_TX n
Characteristics”
SD n _REF_CLK
SD n _REF_CLK
SD1_RX n or
SD2_RX n
SD1_RX n or
SD2_RX n
50 Ω
50 Ω
Clocks”
Receiver
High-Speed Serial Interfaces (HSSI)
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