MPC8245ARZU466D FREESCALE [Freescale Semiconductor, Inc], MPC8245ARZU466D Datasheet - Page 14

• Manufacturer Part Number: MPC8245ARZU466D
• Description: Part Number Specification for the MPC8245ARZUnnnX Series
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

PLL Configuration
14
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. In clock off mode, no clocking occurs inside the MPC8245 regardless of the PCI_SYNC_IN input.
11. Range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for
12. PLL_CFG[0:4] settings not listed are reserved.
13. Multiplier ratios for this PLL_CFG[0:4] setting are different from the MPC8240 and are not
14. PCI_SYNC_IN range for this PLL_CFG[0:4] setting is different from the MPC8240 and may not be fully
15. Bits 7–4 of register offset <0xE2> contain the PLL_CFG[0:4] setting value.
16. In PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral
17. In dual PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal peripheral logic directly, the
Limited by maximum PCI input frequency (66 MHz).
Limited by maximum memory interface operating frequency (133 MHz).
Limited by minimum memory VCO frequency (132 MHz).
Limited due to maximum memory VCO frequency (372 MHz).
Limited by maximum CPU operating frequency (466 MHz).
Limited by minimum CPU VCO frequency (360 MHz).
Limited by maximum CPU VCO frequency (932 MHz).
Limited by minimum CPU operating frequency (100 MHz).
Limited by minimum memory bus frequency (50 MHz).
clarity.
backwards-compatible.
backwards-compatible.
logic PLL is disabled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended for
hardware modeling support. The AC timing specifications given in this document do not apply in the PLL
bypass mode.
peripheral logic PLL is disabled, and the bus mode is set for 1:1 (PCI_SYNC_IN:Mem) mode operation. In
this mode, the OSC_IN input signal clocks the internal processor directly in 1:1 (OSC_IN:CPU) mode
operation, and the processor PLL is disabled. The PCI_SYNC_IN and OSC_IN input clocks must be
externally synchronized. This mode is intended for hardware modeling support. The AC timing specifications
given in this document do not apply in the dual PLL bypass mode.
Ref
1E
1F
Table 19. PLL Configurations for the 466-MHz Part Offering (continued)
MPC8245 Part Number Specification for the MPC8245ARZUnnnX Series, Rev. 2
[0:4]
PLL_CFG
11111
11110
11,14,15
10
PCI Clock Input
(PCI_SYNC_IN)
33
Range
(MHz)
3
–66
1,2
1
466-MHz Part
Not usable
Logic/Mem
Bus Clock
66–132
Periph
Range
(MHz)
9
CPU Clock
231–462
Range
(MHz)
PCI-to-Mem
(Mem VCO)
2 (2)
Off
Multipliers
Freescale Semiconductor
Mem-to-CPU
(CPU VCO)
3.5 (2)
Off