STPCE1EDBI STMICROELECTRONICS [STMicroelectronics], STPCE1EDBI Datasheet - Page 40

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STPCE1EDBI

Manufacturer Part Number
STPCE1EDBI
Description
X86 Core General Purpose PC Compatible System - on - Chip
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
ELECTRICAL SPECIFICATIONS
4.5.3. SDRAM INTERFACE
Figure 4-5
tics of the SDRAM interface. The MCLKx clocks
are the input clock of the SDRAM devices
Table 4-8. SDRAM Bus AC Timing
The PC133 memory is recommended to reach
100MHz operation.
40/87
Note: These timing are for a load of 50pF.
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Toutput
Tsetup
Tdelay
Tcycle
MCLKx
MCLKI
STPC.output
STPC.input
Name
Thigh
Thold
Tlow
and
Parameter
MCLKI Cycle Time
MCLKI High Time
MCLKI Low Time
MCLKI Rising Time
MCLKI Falling Time
MCLKx to MCLKI delay
MCLKI to Outputs Valid
MCLKI to DQM[ ] Outputs Valid
MCLKI to MD[ ] Outputs Valid
MD[63:0] setup to MCKLI without RDCLK
MD[63:0] hold from MCKLI without RDCLK
Table 4-8
T
hold
T
list the AC characteris-
delay
Figure 4-5. SDRAM Timing Diagram
Release 1.3 - January 29, 2002
T
output (max)
T
high
T
cycle
T
setup
T
T
output (min)
low
Min
5.2
4.7
5.1
0.8
0.8
10
4
4
Typ
-2
Max
10.9
10.9
8.7
1.8
1.6
1
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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