XE88LC05MI000 ETC1 [List of Unclassifed Manufacturers], XE88LC05MI000 Datasheet - Page 7

• Manufacturer Part Number: XE88LC05MI000
• Description: 16 + 10 bit Data Acquisition Ultra Low-Power Microcontroller
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

5 Memory organization
5.1 Program memory
Table 5.1:
5.2 Data memory
Table 5.2:
Figure 5.1:
7
0h0000
0h1FFF / 01hBFF
6k instructions ROM
8k instructions MTP
22 bits wide
Program
memory
or
The CPU uses a Harvard architecture, so that memory is organized in two separated fields:
program memory and data memory. As both memories are separated, the central processing
unit can read/write data at the same time it loads an instruction. Peripherals and system control
registers are mapped on data memory space.
Program memory is made in one page. Data is made of several 256 bytes pages.
The program memory is implemented as Multiple Time Programmable (MTP) Flash memory
or ROM. The power consumption of MTP memory is linear with the access frequency (no sig-
nificant static current).
Size of the MTP Flash memory is 8192 x 22 bits (= 22 kBytes)
Size of the ROM memory is 6144 x 22 bits (= 17 kBytes)
Program addresses for MTP or ROM memory
The data memory is implemented as static Random-Access Memory (RAM). The RAM size is
512 x 8 bits plus 8 low power RAM bytes that require very low current when addressed. Pro-
grams using the low-power RAM instead of RAM will use even less current.
RAM addresses
Memory organization
LP RAM
block
block
ROM
RAM
MTP
8192 x 22
6144 x 22
512 x 8
size
size
8 x 8
Data Acquisition Microcontroller
Instruction
pipeline
H0000 - H1FFF
H0000 - H1BFF
H0000 - H0007
H0080 - H027F
address
address
CPU
registers
CPU
RAM
512 Bytes
Peripherals
LP RAM
8 bits wide
XE88LC05
0h0080
0h027F
0h0010
0h0000
D0109-40