XC9572XV-7TQ100I XILINX [Xilinx, Inc], XC9572XV-7TQ100I Datasheet - Page 2

• Manufacturer Part Number: XC9572XV-7TQ100I
• Description: High-performance CPLD
• Manufacturer: XILINX [Xilinx, Inc]

XC9572XV High-performance CPLD
Supported I/O Standards
Table 1: IOSTANDARD Options
The XC9572XV CPLD features both LVCMOS and LVTTL
I/O implementations. See
2
LVTTL
LVCMOS2
X25TO18
IOSTANDARD
Figure 1: Typical ICC vs. Frequency for XC9572XV
Figure 2: XC9572XV Architecture (Function Block outputs (indicated by the bold line) drive the I/O Blocks directly)
JTAG Port
I/O/GCK
I/O/GSR
I/O/GTS
V
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
3.3V
2.5V
1.8V
Table 1
CCIO
for I/O standard voltages.
3
1
1
2
3
Controller
Blocks
JTAG
I/O
www.xilinx.com
The LVTTL I/O standard is a general purpose EIA/JEDEC
standard for 3.3V applications that use an LVTTL input
buffer and Push-Pull output buffer. The LVCMOS2 standard
is used in 2.5V applications.
XC9500XV CPLDs are also 1.8V I/O compatible. The
X25TO18 setting is provided for generating 1.8V compatible
outputs from a CPLD normally operating in a 2.5V environ-
ment. The default I/O Standard for pads without IOSTAN-
DARD attributes is LVTTL for XC9500XV devices.
In-System Programming Controller
18
18
18
18
54
54
54
54
Macrocells
Macrocells
Macrocells
Macrocells
Function
Function
Function
Function
Block 1
Block 2
Block 3
Block 4
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1 to 18
1 to 18
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DS052_02_041200
DS052 (v3.0) June 25, 2007
Product Specification
R