XC95288XV-10PQ208I XILINX [Xilinx, Inc], XC95288XV-10PQ208I Datasheet

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XC95288XV-10PQ208I

Manufacturer Part Number
XC95288XV-10PQ208I
Description
High-Performance CPLD
Manufacturer
XILINX [Xilinx, Inc]
Datasheet

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XC95288XV-10PQ208I
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XILINX
0
DS050 (v2.2) August 27, 2001
Features
Description
The XC95288XV is a 2.5V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of 16
54V18 Function Blocks, providing 6,400 usable gates with
propagation delays of 5 ns.
DS050 (v2.2) August 27, 2001
Advance Product Specification
288 macrocells with 6,400 usable gates
Available in small footprint packages
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Optimized for high-performance 2.5V systems
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Advanced system features
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Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
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© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
144-pin TQFP (117 user I/O pins)
208-pin PQFP (168 user I/O pins)
280-pin CSP (192 user I/O pins)
256-pin FBGA (192 user I/O pins)
Low power operation
Multi-voltage operation
In-system programmable
Four separate output banks
Superior pin-locking and routability with
FastCONNECT II™ switch matrix
Extra wide 54-input Function Blocks
Up to 90 product-terms per macrocell with
individual product-term allocation
Local clock inversion with three global and one
product-term clocks
Individual output enable per output pin
Input hysteresis on all user and boundary-scan pin
inputs
Bus-hold ciruitry on all user pin inputs
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Endurance exceeding 10,000 program/erase
cycles
20 year data retention
ESD protection exceeding 2,000V
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
R
0
0
www.xilinx.com
1-800-255-7778
5
XC95288XV High-Performance
CPLD
Advance Product Specification
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XV device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of I
used:
I
Where:
MC
MC
MC = Total number of macrocells used
f = Clock frequency (MHz)
This calculation is based on typical operating conditions
using a pattern of 16-bit up/down counters in each Function
Block with no output loading. The actual I
with the design application and should be verified during
normal system operation.
Figure 1
CC
Figure 1: Typical I
HP
LP
(mA) =
MC
150
100
450
400
350
300
250
200
50
0
= Macrocells in low-power mode
= Macrocells in high-performance (default) mode
HP
shows the above estimation in a graphical form.
(0.36) + MC
50
CC
LP
Clock Frequency (MHz)
(0.23) + MC(0.005 mA/MHz) f
vs. Frequency for XC95288XV
CC
100
, the following equation may be
120 MHz
150
CC
200
value varies
DS050_01_012501
200 MHz
250
1

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XC95288XV-10PQ208I Summary of contents

Page 1

... ESD protection exceeding 2,000V Description The XC95288XV is a 2.5V CPLD targeted for high-perfor- mance, low-voltage applications in leading-edge communi- cations and computing systems comprised of 16 54V18 Function Blocks, providing 6,400 usable gates with propagation delays of 5 ns. © 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. ...

Page 2

... JTAG Port I/O I/O I/O I/O I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR 4 I/O/GTS (Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.) 2 JTAG In-System Programming Controller Controller I/O Blocks Figure 2: XC95288XV Architecture www.xilinx.com 1-800-255-7778 54 Function 18 Block 1 Macrocells Function 18 Block 2 Macrocells Function 18 Block 3 Macrocells ...

Page 3

... Program/Erase cycles (endurance Electrostatic Discharge (ESD) ESD DS050 (v2.2) August 27, 2001 Advance Product Specification Description (1) (1) Parameter o Commercial Industrial T = –40 A Parameter www.xilinx.com 1-800-255-7778 XC95288XV High-Performance CPLD Value –0.5 to 2.7 –0.5 to 3.6 –0.5 to 3.6 –0.5 to 3.6 –65 to +150 +260 +150 Min Max +70 C 2.37 2. +85 C 2.37 2.62 3.13 3 ...

Page 4

... XC95288XV High-Performance CPLD DC Characteristics Over Recommended Operating Conditions Symbol Parameter V Output high voltage for 3.3V outputs OH Output high voltage for 2.5V outputs Output high voltage for 1.8V outputs V Output low voltage for 3.3V outputs OL Output low voltage for 2.5V outputs Output low voltage for 1.8V outputs I Input leakagelow current ...

Page 5

... Advance Product Specification Output Type V V CCIO TEST 3.3V 3.3V 2.5V 2. 1.8V Figure 3: AC Load Circuit XC95288XV-5 Min Max - 2.0 - 1.2 - 2.0 - 4 1.7 - 0.7 - 5.0 - 0.2 2.0 - 1.5 - 2 0.2 - 5.9 5.0 - 0.7 - 5.7 - 1.6 - 0.7 - 0.3 - 3.0 Advance Information www.xilinx.com 1-800-255-7778 XC95288XV High-Performance CPLD 320 360 35 pF 250 660 35 pF DS052_03_041200 XC95288XV-7 XC95288XV-10 Min Max Min Max Units - 2.3 - 3.5 - 1.5 - 1.8 - 3.1 - 4.5 - 5.0 - 7.0 - 2 2.4 - 2.7 - 1.4 - 1.8 - 7.2 - 7.5 - 1.3 - 1.7 2 ...

Page 6

... XC95288XV High-Performance CPLD XC95288XV I/O Pins Function Macro- Block cell TQ144 PQ208 FG256 ...

Page 7

... R XC95288XV I/O Pins (continued) Function Macro- Block cell TQ144 PQ208 FG256 CS280 (1) ( ...

Page 8

... XC95288XV High-Performance CPLD XC95288XV I/O Pins (continued) Function Macro- Block cell TQ144 PQ208 FG256 CS280 T10 ...

Page 9

... R XC95288XV I/O Pins (continued) Function Macro- Block cell TQ144 PQ208 FG256 CS280 103 P13 106 P15 107 N14 109 R16 110 N15 M15 111 M13 112 P16 113 N16 13 13 ...

Page 10

... XC95288XV High-Performance CPLD XC95288XV Global, JTAG and Power Pins Pin Type TQ144 I/O/GCK1 30 I/O/GCK2 32 I/O/GCK3 38 I/O/GTS1 5 I/O/GTS2 6 I/O/GTS3 2 I/O/GTS4 3 I/O/GSR 143 TCK 67 TDI 63 TDO 122 TMS 65 V 2.5V 8, 42, 84, 141 CCINT V 37 CCIO1 V 1 CCIO2 V 55, 73 CCIO3 V 109, 127 CCIO4 GND 18, 29, 36, 47, 62, 72, ...

Page 11

... Parenthesis indicate future planned products. Please contact Xilinx for up-to-date information. DS050 (v2.2) August 27, 2001 Advance Product Specification XC95288XV -7 TQ 144 C Package 144-pin Thin Quad Flat Pack (TQFP) 208-pin Plastic Quad Flat Pack (PQFP) 256-ball Plastic Fineline Ball Grid Array (FBGA) ...

Page 12

... XC95288XV High-Performance CPLD Revision History Date Version 09/28/98 1.0 Original creation of data sheet. 12/10/98 1.1 Revision of tables. 2/5/99 1.2 Updated pinouts to reflect BG256 (replaces BG352). 6/7/99 1.3 Add -7 speed and CS280 package. 4/11/00 1.4 Updated AC specifications, added bank information to pinout tables. 01/29/01 2.0 Added -5 performance specification, deleted -6; changed BG256 package to FG256 package. Updated I ...

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