ATF1502AS-10JC444 ATMEL [ATMEL Corporation], ATF1502AS-10JC444 Datasheet
ATF1502AS-10JC444
Related parts for ATF1502AS-10JC444
ATF1502AS-10JC444 Summary of contents
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... Pull-up Option on JTAG Pins TMS and TDI • Advanced Power Management Features – Input Transition Detection – Power-down (“L” versions) – Individual Macrocell Power Option – Disable ITD on Global Clocks, Inputs and I/O High- performance EEPROM CPLD ATF1502AS ATF1502ASL Rev. 0995J–PLD–09/02 1 ...
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... PLDs. The ATF1502AS’s enhanced routing switch matrices increase usable gate count and the odds of successful pin-locked design modifications. The ATF1502AS has bi-directional I/O pins and four dedicated input pins, depending on the type of device package selected. Each dedicated pin can also serve as a global control signal, register clock, register reset or output enable ...
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... I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40 individual signals from the global bus. Each macrocell also generates a foldback logic term that goes to a regional bus. Cascade logic between macrocells in the ATF1502AS allows fast, efficient generation of complex logic functions. The ATF1502AS contains four such logic chains, each capable of creating sum term logic with a fan- product terms ...
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... The PTMUX programming is determined by the design compiler, which selects the optimum macrocell configuration. OR/XOR/ The ATF1502AS’s logic structure is designed to efficiently support all types of logic. Within a single macrocell, all the product terms can be routed to the OR gate, creating a 5-input CASCADE Logic AND/OR sum term ...
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... The four foldback terms in each region allow generation of high fan-in sum terms (up to nine product terms) with little additional delay. Programmable The ATF1502AS offers the option of programming all input and I/O pins so that pin-keeper cir- cuits can be utilized. When any pin is driven high or low and then subsequently left floating, it Pin-keeper will stay at that previous high or low level ...
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... This feature may be selected as a design option. The ATF1502AS also has an optional power-down mode. In this mode, current drops to below 10 mA. When the power-down option is selected, either PD1 or PD2 pins (or both) can be used to power down the part ...
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... The ATF1502AS macrocell also has an option whereby the power can be reduced on a per- macrocell basis. By enabling this power-down option, macrocells that are not used in an appli- cation can be turned down, thereby reducing the overall power consumption of the device. ...
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... I/O pins to be used for logic. Contact your local Atmel representatives or Atmel PLD applications for details. ISP The ATF1502AS has a special feature that locks the device and prevents the inputs and I/O from driving if the programming process is interrupted for any reason. The inputs and I/O Programming default to high-Z state during such a condition ...
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... BSC Configuration for Input and I/O Pins (Except JTAG TAP Pins) Note: BSC Configuration for Macrocell 0995J–PLD–09/02 1. The ATF1502AS has a pull-up option on TMS and TDI pins. This feature is selected as a design option. TDO TDI CLOCK OEJ 0 ...
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... PCI Compliance The ATF1502AS also supports the growing need in the industry to support the new Peripheral Component Interconnect (PCI) interface standard in PCI-based designs and specifications. The PCI interface calls for high current drivers, which are much larger than the traditional TTL drivers. In general, PLDs and FPGAs parallel outputs to support the high current load required by the PCI interface ...
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... OUT OUT 0.1 > V > 0 OUT V = 0.71 OUT ≤ < /0.015 0.4V to 2.4V load 1 2.4V to 0.4V load 1 - 5.25 2.45) for V > V > 3.1V. OUT CC OUT * (4 for 0V < V < 0.71V. OUT OUT ATF1502AS(L) Min Max 4.75 5.25 2 0.5 CC -0.5 0.8 70 -70 2.4 0. Max - 1.4) Equation A -142 Equation B 206 + Units V ...
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... Power-down The ATF1502AS includes an optional pin-controlled power-down feature. When this mode is enabled, the PD pin acts as the power-down pin. When the PD pin is high, the device supply Mode current is reduced to less than 5 mA. During power-down, all output data and internal logic states are latched and held. Therefore, all registered and combinatorial output data remain valid ...
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... Com MIN Ind Com MIN 0 Ind MIN -4 ATF1502AS(L) Industrial -40°C - 85°C 5V ± 10% Min Typ Max - -0.3 0.8 2 0.3 CCIO 3.0 0.45 0.45 0.2 0.2 2.4 Units µA µ ...
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... Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. The OGI pin (high-voltage pin during programming) has a maximum capacitance of 12 pF. Timing Model Input Test Waveforms and Measurement Levels Output AC Test Loads ATF1502AS(L) 14 Max Units 1.5 ns typical ...
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... ATF1502AS(L) -25 Max Min Max Units MHz MHz ...
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... Register Preset Time PRE t Register Clear Time CLR t Switch Matrix Delay UIM (2) t Reduced-power Adder RPA Notes: 1. See ordering information for valid part numbers. 2. The t parameter must be added to the t RPA power mode. ATF1502AS(L) 16 (1) -7 Min Max Min pF 0.5 ...
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... 5.25 5.5 60.0 50.0 40.0 30.0 20.0 10.0 0.0 0.00 80.00 100.00 0.0 -10.0 -20.0 -30.0 -40.0 -50.0 -60.0 -70.0 -80.0 -90.0 -100.0 0.00 5.25 5.50 ATF1502AS(L) SUPPLY CURRENT VS. SUPPLY VOLTAGE (T = 25°C, NON-TURBO, BIT6 = 0, BIT 4.00 4.50 4.75 5.00 5.25 5.50 VCC (V) SUPPLY CURRENT VS. FREQUENCY ASL (LOW-POWER) VERSION (T = 25°C) A STANDARD POWER REDUCED POWER 10.00 20.00 30.00 40.00 FREQUENCY (MHz) OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE ( 25° 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 OUTPUT VOLTAGE (V) 6 ...
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... INPUT VOLTAGE (V) OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE (VOL = 0.5V 25° 4.50 4.75 5.00 SUPPLY VOLTAGE (V) NORMALIZED TPD VS. SUPPLY VOLTAGE (T 1.20 1.10 1.00 0.90 0.80 4.5 4.8 5.0 SUPPLY VOLTAGE (V) ATF1502AS( -10 -20 -30 -0.20 0.00 5.25 5.50 = 25°C) A 5.3 5.5 INPUT CURRENT VS. INPUT VOLTAGE ( 25° 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 INPUT VOLTAGE (V) OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE ...
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... NORMALIZED TCO VS. SUPPLY VOLTAGE (T 1.2 1.1 1.0 0.9 0.8 4.5 4.8 5.0 SUPPLY VOLTAGE (V) NORMALIZED TSU VS. SUPPLY VOLTAGE (T 1.2 1.1 1.0 0.9 0.8 4.5 4.8 5.0 SUPPLY VOLTAGE (V) 0995J–PLD–09/02 = 25°C) A 5.3 5.5 = 25°C) A 5.3 5.5 ATF1502AS(L) NORMALIZED TCO VS. TEMPERATURE (V = 5.0V) CC 1.2 1.1 1.0 0.9 0.8 -40.0 0.0 25.0 TEMPERATURE (C) NORMALIZED TSU VS. TEMPERATURE (V = 5.0V) CC 1.2 1.1 1.0 0.9 0.8 -40.0 0.0 25.0 TEMPERATURE (C) 75.0 75.0 19 ...
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... ATF1502AS Dedicated Pinouts Dedicated Pin INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 I/O / GCLK3 I (1,2) I/O / TDI (JTAG) I/O / TMS (JTAG) I/O / TCK (JTAG) I/O / TDO (JTAG) GND VCC # of Signal Pins # User I/O Pins OE (1, 2) Global OE pins GCLR Global Clear pin GCLK ( Global Clock pins PD (1, 2) Power-down pins TDI, TMS, TCK, TDO ...
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... ATF1502AS I/O Pinouts 4/TDI 9/TMS 20/TDO 25/TCK 0995J–PLD–09/02 PLC 44-lead PLCC A/PD1 ...
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... ATF1502AS-10 JC444 ATF1502AS-10 AI44 ATF1502AS-10 JI44 15 8 100 ATF1502AS-15 AC44 ATF1502AS-15 JC44 ATF1502AS-15 AI44 ATF1502AS-15 JI44 ATF1502ASL-25 AC44 ATF1502ASL-25 JC44 ATF1502ASL-25 AI44 ATF1502ASL-25 JI44 Using “C” Product for Industrial To use commercial product for industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device (7 ns “ ...
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... Orchard Parkway San Jose, CA 95131 R 0995J–PLD–09/ TITLE 44A, 44-lead Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) ATF1502AS(L) A COMMON DIMENSIONS (Unit of Measure = mm) MIN SYMBOL NOM MAX NOTE A – – 1.20 A1 0.05 – ...
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... Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. TITLE 2325 Orchard Parkway San Jose, CA 95131 R ATF1502AS(L) 24 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER ...
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Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Room 1219 Chinachem ...