ATF1502AS ATMEL [ATMEL Corporation], ATF1502AS Datasheet - Page 11

• Manufacturer Part Number: ATF1502AS
• Description: High Performance E2PROM CPLD
• Manufacturer: ATMEL [ATMEL Corporation]

Power Down Mode
The ATF1502AS includes an optional pin controlled power
down feature.When this mode is enabled, the PD pin acts
as the power down pin. When the PD pin is high, the device
supply current is reduced to less than 3 mA. During power
down, all output data and internal logic states are latched
and held. Therefore, all registered and combinatorial output
data remain valid. Any outputs which were in a Hi-Z state at
the onset will remain at Hi-Z. During power down, all input
Power Down AC Characteristics
Notes:
Symbol
t
t
t
t
t
t
t
t
t
t
IVDH
GVDH
CVDH
DHIX
DHGX
DHCX
DLIV
DLGV
DLCV
DLOV
1. For slow slew outputs, add t
2. Pin or Product Term.
Parameter
Valid I, I/O Before PD High
Valid OE
Valid Clock
I, I/O Don’t Care After PD High
OE
Clock
PD Low to Valid I, I/O
PD Low to Valid OE (Pin or Term)
PD Low to Valid Clock (Pin or Term)
PD Low to Valid Output
(2)
(2)
Don’t Care After PD High
Don’t Care After PD High
(2)
(2)
Before PD High
Before PD High
SSO
.
(1)(2)
Min
7
7
7
-7
Max
12
12
12
1
1
1
1
Min
10
10
10
signals except the power down pin are blocked. Input and
I/O hold latches remain active to insure that pins do not
float to indeterminate levels, further reducing system
power. The power down pin feature is enabled in the logic
design file. Designs using the power down pin may not use
the PD pin logic array input. However, all other PD pin mac-
rocell resources may still be used, including the buried
feedback and foldback product term array inputs.
-10
Max
15
15
15
1
1
1
1
Min
15
15
15
-15
Max
25
25
25
1
1
1
1
Min
20
20
20
-20
Max
30
30
30
1
1
1
1
Min
25
25
25
-25
Max
35
35
35
1
1
1
1
Units
ns
ns
ns
ns
ns
ns
s
s
s
s
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