ATF1500AS-15AC100 ATMEL [ATMEL Corporation], ATF1500AS-15AC100 Datasheet - Page 4

• Manufacturer Part Number: ATF1500AS-15AC100
• Description: High- Performance EE CPLD
• Manufacturer: ATMEL [ATMEL Corporation]

TTL, SSI, MSI, LSI and classic PLDs. The ATF1504AS’s
enhanced routing switch matrices increase usable gate
count, and the odds of successful pin-locked design modifi-
cations.
The ATF1504AS has up to 68 bi-directional I/O pins and 4
dedicated input pins, depending on the type of device pack-
age selected. Each dedicated pin can also serve as a glo-
bal control signal; register clock, register reset or output
enable. Each of these control signals can be selected for
use individually within each macrocell.
Each of the 64 macrocells generates a buried feedback,
which goes to the global bus. Each input and I/O pin also
feeds into the global bus. The switch matrix in each logic
Block Diagram
Unused product terms are automatically disabled by the
compiler to decrease power consumption. A Security Fuse,
w h e n p r o g r a m m e d , p r o t e c t s t h e c o n t e n t s o f t h e
ATF1504AS. Two bytes (16-bits) of User Signature are
accessible to the user for purposes such as storing project
name, part number, revision or date. The User Signature is
accessible regardless of the state of the Security Fuse.
4
ATF1504ASZ
block then selects 40 individual signals from the global bus.
Each macrocell also generates a foldback logic term, which
goes to a regional bus. Cascade logic between macrocells
in the ATF1504AS allows fast, efficient generation of com-
plex logic functions. The ATF1504AS contains four such
logic chains, each capable of creating sum term logic with a
fan in of up to 40 product terms.
The ATF1504AS macrocell shown in Figure 1, is flexible
enough to support highly complex logic functions operating
at high speed. The macrocell consists of five sections:
product terms and product term select multiplexer;
OR/XOR/CASCADE logic; a flip-flop; output select and
enable; and logic array inputs.
The ATF1504AS device is an In-System Programmable
(ISP) device. It uses the industry standard 4-pin JTAG
interface (IEEE Std. 1149.1), and is fully compliant with
JTAG’s Boundary Scan Description Language (BSDL). ISP
allows the device to be programmed without removing it
from the printed circuit board. In addition to simplifying the
manufacturing flow, ISP also allows design modifications to
be made in the field via software.