AD5421_11 AD [Analog Devices], AD5421_11 Datasheet - Page 19

• Manufacturer Part Number: AD5421_11
• Description: 16-Bit, Serial Input, Loop-Powered, 4 mA to 20 mA DAC
• Manufacturer: AD [Analog Devices]

THEORY OF OPERATION
The AD5421 is an integrated device designed for use in loop-
powered, 4 mA to 20 mA smart transmitter applications. In a
single chip, the AD5421 provides a 16-bit DAC and current
amplifier for digital control of the loop current, a voltage
regulator to power the entire transmitter, a voltage reference,
fault alert functions, a flexible SPI-compatible serial interface,
gain and offset adjust registers, as well as other features and
functions. The features of the AD5421 are described in the
following sections.
FAULT ALERTS
The AD5421 provides a number of fault alert features. All
faults are signaled to the controller via the FAULT pin and the
fault register. In the case of a loss of communication between
the AD5421 and the microcontroller (SPI fault), the AD5421
programs the loop current to an alarm value. If the controller
detects that the FAULT pin is set high, it should then read the
fault register to determine the cause of the fault.
SPI Fault
The SPI fault is asserted if there is no valid communication to
any register of the AD5421 for more than a user-defined period.
The user can program the time period using the SPI watchdog
timeout bits of the control register. The SPI fault bit of the fault
register indicates the fault on the SPI bus. Because this fault is
caused by a loss of communication between the controller and
the AD5421, the loop current is also forced to the alarm value.
The direction of the alarm current (downscale or upscale)
is selected via the ALARM_CURRENT_DIRECTION pin.
Connecting this pin to DV
(22.8 mA/24 mA); connecting this pin to COM selects a
downscale alarm current (3.2 mA).
Packet Error Checking
To verify that data has been received correctly in noisy environ-
ments, the AD5421 offers the option of error checking based on
an 8-bit cyclic redundancy check (CRC). Packet error checking
(PEC) is enabled by writing to the AD5421 with a 32-bit serial
frame, where the least significant eight bits are the frame check
sequence (FCS). The device controlling the AD5421 should
generate the 8-bit FCS using the following polynomial:
The 8-bit FCS is appended to the end of the data-word, and
32 data bits are sent to the AD5421 before SYNC is taken high.
If the check is valid, the data is accepted. If the check fails, the
FAULT pin is asserted and the PEC bit of the fault register is set.
After the fault register is read, the PEC bit is reset low and the
FAULT pin returns low.
C( x ) = x
8
+ x
2
+ x + 1
DD
selects an upscale alarm current
Rev. 0 | Page 19 of 32
In the case of data readback, if the AD5421 is addressed with a
32-bit frame, it generates the 8-bit frame check sequence and
appends it to the end of the 24-bit data stream to create a 32-bit
data stream.
Current Loop Fault
The current loop (I
current is not within ±0.01% FSR of the programmed loop
current. If the measured loop current is less than the programmed
loop current, the I
measured loop current is greater than the programmed loop
current, the I
pin is set to logic high in either case.
An I
sourced from the AD5421 (via REG
or DV
to flow in the loop. An I
is insufficient compliance voltage to support the programmed
loop current, caused by excessive load resistance or low loop
supply voltage.
Overtemperature Fault
There are two overtemperature alert bits in the fault register:
Temp 100°C and Temp 140°C. If the die temperature of the
AD5421 exceeds either 100°C or 140°C, the appropriate bit is
set. If the Temp 140°C bit is set in the fault register, the FAULT
pin is set to logic high.
FAULT
SYNC
SYNC
SCLK
SCLK
SDIN
SDIN
LOOP
DD
Over condition occurs when the value of the load current
) is greater than the loop current that is programmed
MSB
MSB
D23
D31
LOOP
24-BIT DATA TRANSFER—NO ERROR CHECKING
32-BIT DATA TRANSFER WITH ERROR CHECKING
Over bit of the fault register is set. The FAULT
LOOP
LOOP
UPDATE ON SYNC HIGH
Under bit of the fault register is set. If the
Figure 39. PEC Timing
) fault is asserted when the actual loop
24-BIT DATA
24-BIT DATA
LOOP
Under condition occurs when there
ONLY IF ERROR CHECK PASSED
UPDATE AFTER SYNC HIGH
OUT
IF ERROR CHECK FAILS
LSB
LSB
FAULT PIN GOES HIGH
D0
D8
, REFOUT1, REFOUT2,
D7
8-BIT FCS
AD5421
D0