AD844_07 AD [Analog Devices], AD844_07 Datasheet - Page 10

• Manufacturer Part Number: AD844_07
• Description: 60 MHz, 2000 V/us Monolithic Op Amp
• Manufacturer: AD [Analog Devices]

AD844
Input Impedance
At low frequencies, negative feedback keeps the resistance at the
inverting input close to zero. As the frequency increases, the
impedance looking into this input will increase from near zero to
the open loop input resistance, due to bandwidth limitations,
making the input seem inductive. If it is desired to keep the
input impedance flatter, a series RC network can be inserted
across the input. The resistor is chosen so that the parallel sum
of it and R2 equals the desired termination resistance. The
capacitance is set so that the pole determined by this RC network
is about half the bandwidth of the op amp. This network is not
important if the input resistor is much larger than the termina-
tion used, or if frequencies are relatively low. In some cases, the
small peaking that occurs without the network can be of use in
extending the –3 dB bandwidth.
Driving Large Capacitive Loads
Capacitive drive capability is 100 pF without an external net-
work. With the addition of the network shown in Figure 7, the
capacitive drive can be extended to over 10,000 pF, limited by
internal power dissipation. With capacitive loads, the output
speed becomes a function of the overdriven output current
limit. Since this is roughly ± 100 mA, under these conditions,
the maximum slew rate into a 1000 pF load is ± 100 V/µs.
Figure 8 shows the transient response of an inverting amplifier
(R1 = R2 = 1 kΩ) using the feed forward network shown in
Figure 7, driving a load of 1000 pF.
Settling Time
Settling time is measured with the circuit of Figure 9. This
circuit employs a false summing node, clamped by the two
AD844
750
22pF
C
L
V
OUT
Schottky diodes, to create the error signal and limit the input
signal to the oscilloscope. For measuring settling time, the ratio
of R6/R5 is equal to R1/R2. For unity gain, R6 = R5 = 1 kΩ,
and R
and R
output with approximately 275 Ω. Using this network in a
unity-gain configuration, settling time is 100 ns to 0.1% for a
–5 V to +5 V step with C
DC Error Calculation
Figure 10 shows a model of the dc error and noise sources for
the AD844. The inverting input bias current, I
feedback resistor. I
in the resistance at Pin 3 (R
any offset voltage) will appear at the inverting input. The total
error, V
Since I
inserting a resistor in series with the noninverting input will not
necessarily reduce dc error and may actually increase it.
R2
V
L
L
V
BN
O
IN
O
= 500 Ω. For the gain of –10, R5 = 50 Ω, R6 = 500 Ω
was not used since the summing network loads the
, at the output is:
= (I
+
and I
V
~
N
BP
D1, D2 IN6263 OR EQUIV. SCHOTTKY DIODE
R3
BP
R
R
R5
D1
are unrelated both in sign and magnitude,
BP
P
I
P
I
NN
NP
, the noninverting input bias current, flows
+ V
R2
OS
L
= 10 pF.
+ I
TO SCOPE
(TEK 7A11 FET PROBE)
D2
P
), and the resulting voltage (plus
AD844
BN
I
I
R
BN
BP
IN
R
AD844
IN
R6
) 1 +



R1
V
OS
R
R1
L
R2
R1
BN

 + I

, flows in the
BN
C
V
L
OUT
R1