AD7366-5ARUZ AD [Analog Devices], AD7366-5ARUZ Datasheet - Page 16

• Manufacturer Part Number: AD7366-5ARUZ
• Description: True Bipolar Input, Dual 1us, 12-Bit, 2-Channel SAR ADC
• Manufacturer: AD [Analog Devices]

AD7366
SERIAL INTERFACE
Figure 9 shows the detailed timing diagram for serial inter-
facing to the AD7366. On the falling edge of CONVST the
AD7366 will simultaneously convert the selected channels.
These conversions are performed using the on-chip oscillator.
After the falling edge of CONVST the BUSY signal goes high,
indicating the conversion has started. It returns low once the
conversion has been completed. The data can now be read from
the
AD7366. The AD7366 has two output pins corresponding to
each ADC. Data can be read from the AD7366 using both
D
choice can be used. The SCLK input signal provides the
clock source for the serial interface. The CS goes low to
access data from the AD7366. The falling edge of CS takes
the bus out of three-state and clocks out the MSB of the
conversion result. The data stream consists of 12 bits of data
MSB first. The first bit of the conversion result is valid on the
first SCLK falling edge after the CS falling edge. The
subsequent 11 bits of data are clocked out on the falling edge
of the SCLK signal. A minimum of 12 Clock pulses must be
provided to AD7366 to access each conversion result.
D OUT A
D OUT B
D
CS and SCLK signals are required to transfer data from the
SCLK
OUT
SCLK
OUT
CS
CS
D
A
A & D
OUT
THREE-
STATE
3-STATE
pins.
OUT
DB11
B, alternatively a single output pin of your
DB11
1
A
DB10
t
t
4
1
4
DB10
A
2
DB9
2
A
DB9
3
Figure 10. Reading Data from Both ADC’s on ONE D
3
DB8
4
t
t
8
5
4
t
5
7
t
5
t
8
Figure 9. Serial Interface Timing diagram
5
10
Figure
DB1
Rev. PrG | Page 16 of 17
t
6
t
6
A
11
DB0
A
9
results.
On the rising edge of CS , the conversion will be terminated
and D
brought high, but is instead held low for a further 12 SCLK
cycles on either D
ADC follows on the D
where the case for D
line in use goes back into three-state on the rising edge of CS
If the falling edge of SCLK coincides with the falling edge of
CS , then the falling edge of SCLK is not acknowledged by
the AD7366, and the next falling edge of the SCLK will be
the first registered after the falling edges of the CS .
The CS pin can be brought low before the BUSY signal goes
low to indicate the end of a conversion. The data bus is bought
out of three-state by taking the CS pin low. This feature can be
utilized to ensure that the MSB is valid on the falling edge of
BUSY by bring CS low a minimum of t
BUSY signal goes low. The dotted
this.
12
DB11
shows how a 12 SCLK read is used to access the conversion
DB2
B
OUT
OUT
13
DB10
t
7
A and D
Line with 28 SCLK’s
DB1
B
OUT
OUT
Preliminary Technical Data
DB0
OUT
t
B go back into three-state. If CS is not
A or D
9
OUT
A is shown. In this case, the D
12
pin. This is illustrated in
OUT
3-STATE
B, the data from the other
DB1
CS line
B
4
nanoseconds before the
in Figure 7 illustrates
DB0
B
24
t
10
Figure 10
THREE-
STATE
OUT