CDP6402CDX INTERSIL [Intersil Corporation], CDP6402CDX Datasheet - Page 11

• Manufacturer Part Number: CDP6402CDX
• Description: CMOS Universal Asynchronous Receiver/Transmitter (UART)
• Manufacturer: INTERSIL [Intersil Corporation]

NOTES:
NOTES:
1. The holding register is loaded on the trailing edge of TBRL.
2. The transmitter shift register, if empty, is loaded on the first high-to-low transition of the clock which occurs at least 1/2 clock period + t
1. If a start bit occurs at a time less than t
2. If a pending DA has not been cleared by a read of the receiver holding register by the time a new word is loaded into the receiver holding
after the trailing edge of TBRL and transmission of a start bit occurs 1/2 clock period + t
high-to-low transition of the clock. The start bit may be completely asynchronous with the clock.
register, the OE signal will come true.
R BUS 0 -
(NOTE 2)
R BUS 7
RRC
DRR
RRI
T BUS 0
T BUS 7
DR
OE
PE
FE
(NOTE 1)
t
TBRE
CH
TBRL
TRO
TRC
TRE
t
DC
t
CC
t
CL
1
t
CH
2
t
THC
t
t
TTHR
t
THTH
CC
t
DC
DT
FIGURE 7. TRANSMITTER TIMING WAVEFORMS
3
START BIT PARITY
t
DATA
FIGURE 8. RECEIVER TIMING WAVEFORMS
before a high-to-low transition of the clock, the start bit may not be recognized until the next
CL
4
CLOCK 7 1/2
t
TD
CDP6402, CDP6402C
SAMPLE
5
t
t
DDA
DD
1
TRANSMITTER BUFFER
REGISTER LOADED
(NOTE 1)
TRANSMITTER SHIFT
REGISTER LOADED
(NOTE 2)
t
6
TTS
2
t
CD
t
7
CT
5-84
3
16
4
STOP BIT 1
1
5
2
6
HOLDING REGISTER
3
CLOCK 7 1/2 LOAD
7
CD
4
14
later.
5
15
t
COE
6
t
t
CPE
16
CFE
7
1
1ST DATA BIT
8
2
t
CD
DATA
9
t
t
CDA
CDV
3
THC