M4T32-BR12SH STMICROELECTRONICS [STMicroelectronics], M4T32-BR12SH Datasheet - Page 11

• Manufacturer Part Number: M4T32-BR12SH
• Description: 5.0 OR 3.0V, 512 bit 64 x 8 SERIAL RTC and NVRAM SUPERVISOR
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Figure 13. Alternate READ Mode Sequence
WRITE Mode
In this mode the master transmitter transmits to
the M41ST85Y/W slave receiver. Bus protocol is
shown in
START condition and slave address, a logic '0' (R/
W=0) is placed on the bus and indicates to the ad-
dressed device that word address An will follow
and is to be written to the on-chip address pointer.
The data word to be written to the memory is
Figure 14. WRITE Mode Sequence
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
Figure 14., page
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
S
ADDRESS
SLAVE
S
ADDRESS
SLAVE
11. Following the
ADDRESS (An)
WORD
DATA n
strobed in next and the internal address pointer is
incremented to the next memory location within
the RAM on the reception of an acknowledge
clock. The M41ST85Y/W slave receiver will send
an acknowledge clock to the master transmitter af-
ter it has received the slave address (see
11., page
word address and each data byte.
DATA n
DATA n+1
10) and again after it has received the
DATA n+1
M41ST85Y, M41ST85W
DATA n+X
DATA n+X
AI00895
AI00591
P
P
Figure
11/34