AD7304BN AD [Analog Devices], AD7304BN Datasheet - Page 12

• Manufacturer Part Number: AD7304BN
• Description: +3 V/+5 V, Rail-to-Rail Quad, 8-Bit DAC
• Manufacturer: AD [Analog Devices]

AD7304/AD7305
AD7304 Hardware Shutdown SHDN
If a three-state driver is used on the SDI/SHDN pin, the AD7304
can be placed into a power shutdown mode when the SDI/
SHDN pin is placed in a high impedance state. For proper
operation no other termination voltages should be present on
this pin. An internal window comparator will detect when the
logic voltage on the SHDN pin is between 28% and 36% of
V
voltage on the SHDN pin. The four DAC output voltages be-
come high impedance with a nominal resistance of 120 kΩ to
ground. See Figure 30 for an equivalent circuit.
AD7304/AD7305 POWER ON RESET
When the V
strobe forces all the Input and DAC registers to the zero-code
state. The V
creasing ramp in order to have consistent results, especially in
the region of V
on the power ON reset performance. The DAC register data
will stay at zero until a valid serial register software load takes
place. In the case of the double buffered AD7305 the output
DAC register can only be changed once the LDAC strobe is
initiated.
AD7305 PARALLEL DATA INTERFACE
The AD7305 has an 8-bit parallel interface DB7 = MSB,
DB0 = LSB. Two address Bits A1 and A0 are decoded when an
active low write strobe is placed on the WR pin, see Table III.
The WR is a level-sensitive input pin, therefore the data setup
and data hold times defined in the TIMING SPECIFICATIONS
need to be adhered to.
The LDAC pin provides the capability of simultaneously updat-
ing all DAC registers with new data from the Input Registers at
CLK
SDI
DD
CS
. A high impedance internal bias generator provides this
EN
Figure 31. AD7304 Equivalent Logic Interface
80k
280k
640k
SDC
SAC
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
DD
DD
2:4
DECODE
GND
320k
DD
680k
8
power supply should have a monotonically in-
power supply is turned on, an internal reset
V
DACA
= 1.5 V to 2.3 V. The V
DD
B
C
D
V
REF
A V
g
D Q
g
D Q
g
D Q
g
D Q
REGISTER
REGISTER
REGISTER
REGISTER
POWER-
RESET
INPUT
INPUT
INPUT
INPUT
ON
REF
B V
AD7304
R
R
R
R
REF
LDAC
C V
REGISTER
REGISTER
REGISTER
REGISTER
SS
REF
DAC A
DAC B
DAC C
DAC D
supply has no effect
D
R
R
R
R
V
CLR
DD
DAC A
DAC B
DAC C
DAC D
OE
OE
OE
OE
V
SS
V
V
V
V
OUT
OUT
OUT
OUT
A
B
C
D
–12–
the same time. This will result in the analog outputs all chang-
ing to their new values at the same time. The LDAC pin is a
level-sensitive input. If the simultaneous update feature is not
required the LDAC pin can be tied to logic low. When the
LDAC is tied to logic low, the DAC Registers become transpar-
ent and the Input Register data determines the DAC output
voltage. See Figure 32 for an equivalent interface logic diagram.
AD7226 Pin Compatibility
By tying the LDAC pin to ground, the AD7305 has the same
pin out and functionality as the AD7226, with the exception of
a lower power supply operating voltage.
AD7305 Hardware Shutdown SHDN
If a three state driver is used on the A0/SHDN pin, the AD7305
can be placed into a power shutdown mode when the A0/SHDN
pin is placed in a high impedance state. For proper operation no
other termination voltages should be present on this pin. An
internal window comparator will detect when the logic voltage
on the SHDN pin is between 28% and 36% of V
impedance internal bias generator provides this voltage on the
SHDN pin. The four DAC output voltages become high imped-
ance with a nominal resistance of 120 kΩ to ground.
ESD Protection Circuits
All logic input pins contain back-biased ESD protection Zeners
connected to ground (GND). The V
back-biased ESD protection Zener connected to V
Figure 33).
DB0–DB7
A0/SHDN
DATA
WR
A1
DIGITAL
INPUTS
Figure 32. AD7305 Equivalent Logic Interface
Figure 33. Equivalent ESD Protection Circuits
280k
640k
80k
8
2:4
DECODE
GND
DAC A
GND
680k
320k
V
DD
B
C
D
REGISTER
REGISTER
REGISTER
REGISTER
POWER-
RESET
INPUT
INPUT
INPUT
INPUT
ON
AD7305
R
R
R
R
V
V
REF
LDAC
DD
REF
X
pins also contain a
REGISTER
REGISTER
REGISTER
REGISTER
DAC A
DAC B
DAC C
DAC D
V
REF
R
R
R
R
V
DD
DD
DAC C
DAC D
DAC A
DAC B
. A high
DD
OE
OE
OE
OE
V
SS
(see
REV. A
V
V
V
V
OUT
OUT
OUT
OUT
A
B
C
D