S29GL128S SPANSION [SPANSION], S29GL128S Datasheet
S29GL128S
Available stocks
Related parts for S29GL128S
S29GL128S Summary of contents
Page 1
... S29GL01GS 1 Gbit S29GL512S 512 Mbit S29GL256S 256 Mbit S29GL128S 128 Mbit CMOS 3.0 Volt Core with Versatile I/O Data Sheet Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production ...
Page 2
Notice On Data Sheet Designations Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all ...
Page 3
... GL-S MirrorBit Non-Volatile Memory Family S29GL01GS 1 Gbit S29GL512S 512 Mbit S29GL256S 256 Mbit S29GL128S 128 Mbit CMOS 3.0 Volt Core with Versatile I/O Data Sheet General Description ® The Spansion S29GL01G/512/256/128S are MirrorBit Eclipse flash products fabricated process technology. These devices offer a fast page access time as fast with a corresponding random access time as fast as 90 ns. They feature a Write Buffer that allows a maximum of 256 words/512 bytes to be programmed in one operation, resulting in faster effective programming time than standard programming algorithms. This makes these devices ideal for today’ ...
Page 4
Performance Summary Density 128 Mb 256 Mb 512 Buffer Programming (512 bytes) Sector Erase (128 kbytes) Active Read at 5 MHz Maximum Read Access Times ...
Page 5
Table of Contents General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 6
Power-On Reset (POR) and Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 7
Figures Figure 1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 8
... Table 2.1 S29GL01GS Sector and Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 2.2 S29GL512S Sector and Memory Address Map Table 2.3 S29GL256S Sector and Memory Address Map Table 2.4 S29GL128S Sector and Memory Address Map Table 2.5 ID-CFI Address Map Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 2.6 Secure Silicon Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 3.1 Sector Protection States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 3 ...
Page 9
Table 10.7 Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 10
Product Overview The GL-S family consists of 128-Mbit to 1Gbit, 3.0V core, Versatile I/O, non-volatile, flash memory devices. These devices have a 16-bit (word) wide data bus and use only word boundary addresses. All read accesses provide 16 bits ...
Page 11
Address within Page Address within Write Buffer Page Write-Buffer-Line Sector The device control logic is subdivided into two parallel operating sections, the Host Interface Controller (HIC) and the Embedded Algorithm Controller (EAC). HIC monitors signal levels on the device inputs ...
Page 12
Software Interface 2. Address Space Maps There are several separate address spaces that may appear within the address range of the flash memory device. One address space is visible (entered) at any given time. Flash Memory Array: the main ...
Page 13
While in EA mode, only the Program / Erase suspend command or the Status Register Read command will be accepted. All other commands are ignored. Thus, no other ASO may be entered from the EA mode. When an Embedded Algorithm ...
Page 14
... JEDEC Manufacturer ID (Autoselect) and Common Flash Interface (CFI) information, respectively. Word Address (SA) + 0000h to 000Fh (SA) + 0010h to 0079h (SA) + 0080h to FFFFh For the complete address map see Table 2.4 S29GL128S Sector and Memory Address Map Sector Count Sector Range SA00 128 : SA127 Table 2.5 ID-CFI Address Map Overview Description ...
Page 15
Device ID The Joint Electron Device Engineering Council (JEDEC) standard JEP106T defines the manufacturer ID for a compliant memory. Common industry usage defined a method and format for reading the manufacturer ID and a device specific ID from a ...
Page 16
Data Polling Status ASO The Data Polling Status ASO contains a single word of volatile memory indicating the progress of an EA. The Data Polling Status ASO is entered immediately following the last write cycle of any command sequence ...
Page 17
Sector Protection Control 2.6.1 Lock Register ASO The Lock register ASO contains a single word of OTP memory. When the ASO is entered the Lock Register appears at all word locations in the device address space. However ...
Page 18
Data Protection The device offers several features to prevent malicious or accidental erasure of any sector via hardware means. 3.1 Device Protection Methods 3.1.1 Power-Up Write Inhibit RESET#, CE#, WE#, and, OE# are ignored during Power-On Reset (POR). During ...
Page 19
Sector Protection Methods 3.4.1 Write Protect Signal If WP the lowest or highest address sector is protected from program or erase operations independent IL of any other ASP configuration. Whether it is the lowest or highest ...
Page 20
There is no command in the Persistent Protection method to set the PPB Lock bit therefore the PPB Lock bit will remain at 0 until the next power-off or hardware reset. The Persistent Protection method allows boot code the option ...
Page 21
Sector Protection States Summary Each sector can be in one of the following protection states: Unlocked – The sector is unprotected and protection can be changed by a simple command. The protection state defaults to unprotected after a ...
Page 22
If both lock bits are selected to be programmed at the same time, the operation will abort. Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently disabled and no changes to the protection scheme ...
Page 23
The Password Unlock command cannot be accepted any faster than once every 100 µs ± 20 µs. This makes it take an unreasonably long time (58 million years) for a hacker to run through all the 64-bit combinations in ...
Page 24
Read Operations 4.1 Asynchronous Read Each read access may be made to any location in the memory (random access). Each random access is self- timed with the same latency from CE# or address to valid data (t 4.2 Page ...
Page 25
Embedded Operations 5.1 Embedded Algorithm Controller (EAC) The EAC takes commands from the host system for programming and erasing the flash memory array and performs all the complex operations needed to change the non-volatile memory state. This frees the ...
Page 26
Program and Erase Summary Flash data bits are erased in parallel in a large group called a sector. The Erase operation places each data bit in the sector in the logical 1 state (High). Flash data bits may be ...
Page 27
Write Buffer Programming more efficient and thus faster than programming individual words with the Word Programming command. 5.2.2 Incremental Programming The same word location may be programmed more than once, by either the Word or Write Buffer ...
Page 28
Write Buffer Programming A write buffer is used to program data within a 512-byte address range aligned on a 512-byte boundary (Line). Thus, a full Write Buffer Programming operation must be aligned on a Line boundary. Programming operations of ...
Page 29
In this case the same area will need to be reprogrammed with the same data or erased to ensure data values are properly programmed or erased. Figure 5.2 Write Buffer Programming Operation with Data ...
Page 30
Figure 5.3 Write Buffer Programming Operation with Status Register Program aborted during Write to Buffer command Notes: 1. See Table 6.1, Command Definitions on page 57 2. When Sector Address is specified, any address in the selected sector is acceptable. ...
Page 31
Sequence Issue Unlock Command 1 Issue Unlock Command 2 Issue Write to Buffer Command at Sector Address Issue Number of Locations at Sector Address Example words to pgm words to ...
Page 32
Program operations can be interrupted as often as necessary but in order for a program operation to progress to completion there must be some periods of time between resume and the next suspend command greater than or equal to t ...
Page 33
Sector Erase The sector erase function erases one sector in the memory array. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire sector for an all ...
Page 34
Erase Suspend / Erase Resume The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, the main flash array. This command is valid only during sector erase ...
Page 35
ASO Entry and Exit 5.3.6.1 ID-CFI ASO The system can access the ID-CFI ASO by issuing the ID-CFI Entry command sequence during Read Mode. This entry command uses the Sector Address (SA) in the command to determine which sector ...
Page 36
Lock Register ASO The system can access the Lock Register by issuing the Lock Register entry command sequence during Read Mode. This entry command does not use a sector address from the entry command. The Lock Register appears at ...
Page 37
DYB ASO The system can access the DYB ASO by issuing the DYB entry command sequence during Read Mode. This entry command does not use a sector address from the entry command. The DYB bit for a sector appears ...
Page 38
Program Suspended (bit 2), The current state bits indicate whether process, suspended, or completed. The upper 8 bits (bits 15:8) are reserved. These have undefined High or Low value that can change from one status ...
Page 39
DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or has completed. Data# Polling is valid after the rising edge of the final WE# pulse in the program ...
Page 40
DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Program Suspend or Erase Suspend mode. Toggle Bit I may ...
Page 41
Reading Toggle Bits DQ6/DQ2 Refer to Figure 5.5 on page 39 toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store ...
Page 42
DQ1: Write-to-Buffer Abort DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a 1. The system must issue the Write-to-Buffer-Abort-Reset command sequence to return the EAC to standby (read mode) and the Status Register failed ...
Page 43
Embedded Operation Error If an error occurs during an embedded operation (program, erase, blank check, or password unlock) the device (EAC) remains busy. The RY/BY# output remains Low, data polling status continues to be overlaid on all address locations, ...
Page 44
Protection Error If an embedded algorithm attempts to change data within a protected area (program, or erase of a protected sector or OTP area) the device (EAC) goes busy for a period 100 µs then returns ...
Page 45
Write Buffer Abort If an error occurs during a Write to Buffer command the device (EAC) remains busy. The RY/BY# output remains Low, data polling status continues to be overlaid on all address locations, and the status register shows ...
Page 46
Embedded Algorithm Performance Table Parameter Sector Erase Time 128 kbyte Single Word Programming Time Buffer Programming Time Effective Write Buffer Program Operation per Word Sector Programming Time 128 kB (full Buffer Programming) Erase Suspend/Erase Resume (t Program Suspend/Program Resume ...
Page 47
Parameter Sector Erase Time 128 kbyte Single Word Programming Time Buffer Programming Time Effective Write Buffer Program Operation per Word Sector Programming Time 128 kB (full Buffer Programming) Erase Suspend/Erase Resume (t Program Suspend/Program Resume (t Erase Resume to next ...
Page 48
Command State Transitions Command Current State Read and Condition Address RA Data RD - READ READ Read Protect = False READSR - (return) Table 5.7 Read Unlock Command State Transition Status Command Current Register and Read State Read Condition ...
Page 49
Table 5.9 Erase Suspend State Command Transition Command and Current State Condition Address Data ESR (1) - SR( SR( ESSR - Note: 1. State will automatically move to ES state by t ESL Table 5.10 ...
Page 50
Table 5.12 Erase Suspend - Program Command State Transition Current State Command Read and Condition Address RA Data RD WC > 256 or SA ≠ SA ES_WB ES_WB WC ≤ 256 and < Write ...
Page 51
Command Software Current and Read Reset / ASO State Condition Address RA Data RD WC > 256 or SA ≠ ≤ 256 and Write Buffer ≠ Write Buffer WB_D WB_D ...
Page 52
Table 5.17 Lock Register State Command Transition Command Current State and Read Condition Address RA Data LRPG1 - LRPG1 LRPG - LRPG LRSR - (return) LREXT - LREXT Command and Current State Condition Address Data CFI ...
Page 53
Table 5.21 Secure Silicon Sector Program State Command Transition Command and Current State Condition Address Data SSRPG1 - WC > 256 or SA ≠ SA SSR_WB WC ≤ 256 and < Write Buffer ≠ ...
Page 54
Table 5.23 Non-Volatile Protection Command State Transition Command Software Current and Read Reset / State Condition ASO Exit Address RA xh Data RD xF0h PPB - PPB READ PPBPG1 - PPBPG1 READ SR( PPBPG PPBPG SR(7) = ...
Page 55
Current State Command Transition BLCK Table 5.8 CER Table 5.8 CFI Table 5.18 CFISR Table 5.18 DYB Table 5.25 DYBEXT Table 5.25 DYBSET Table 5.25 DYBSR Table 5.25 ER Table 5.8 ERSR Table 5.8 ERUL1 Table 5.8 ERUL2 Table 5.8 ...
Page 56
Current State Command Transition PPBPG1 Table 5.23 PPBSR Table 5.23 PPD Table 5.22 PPEXT Table 5.22 PPPG Table 5.22 PPPG1 Table 5.22 PPSR Table 5.22 PS Table 5.16 PSR Table 5.16 PSSR Table 5.16 PPWB25 Table 5.22 READ Table 5.6 ...
Page 57
Software Interface Reference 6.1 Command Summary Command Sequence First (Note 1) Addr Data Read (Note Reset/ASO Exit (Notes 7, 16) 1 XXX F0 Status Register Read 2 555 70 Status Register Clear 1 555 71 ...
Page 58
Command Sequence First (Note 1) Addr Data Lock Register Entry 3 555 Program (Note 15) 2 XXX Read (Note 15 Command Set Exit 2 XXX (Notes 12, 16) Reset/ASO Exit 1 XXX (Notes 7, 16) Password ASO Entry ...
Page 59
Command Sequence First (Note 1) Addr Data DYB ASO Entry 3 555 AA DYB Set (Note 17) 2 XXX A0 DYB Clear (Note 17) 2 XXX A0 DYB Status Read (0) (Note 17) Command Set Exit 2 ...
Page 60
Device ID and Common Flash Interface (ID-CFI) ASO Map The Device ID portion of the ASO (word locations 0h to 0Fh) provides manufacturer ID, device ID, Sector Protection State, and basic feature set information for the device. ID-CFI Location ...
Page 61
Word Address (SA) + 0010h (SA) + 0011h (SA) + 0012h (SA) + 0013h (SA) + 0014h (SA) + 0015h (SA) + 0016h (SA) + 0017h (SA) + 0018h (SA) + 0019h (SA) + 001Ah Word Address (SA) + 001Bh ...
Page 62
Word Address (SA) + 0027h (SA) + 0028h (SA) + 0029h (SA) + 002Ah (SA) + 002Bh (SA) + 002Ch (SA) + 002Dh (SA) + 002Eh (SA) + 002Fh (SA) + 0030h (SA) + 0031h (SA) + 0032h (SA) + ...
Page 63
Table 6.6 CFI Primary Vendor-Specific Extended Query (Sheet Word Address (SA) + 0040h (SA) + 0041h (SA) + 0042h (SA) + 0043h (SA) + 0044h (SA) + 0045h (SA) + 0046h (SA) + 0047h (SA) + 0048h ...
Page 64
Table 6.6 CFI Primary Vendor-Specific Extended Query (Sheet Word Address (SA) + 004Fh (SA) + 0050h (SA) +0051h (SA) + 0052h (SA) + 0053h (SA) + 0054h (SA) + 0055h (SA) + 0056h (SA) + 0078h (SA) ...
Page 65
... IL transfer is from device to host. Address inputs. A25-A0 for S29GL01GS A24-A0 for S29GL512S A23-A0 for S29GL256S A22-A0 for S29GL128S Data inputs and outputs Write Protect disables program and erase functions in the lowest or highest address IL 64-kword (128-kB) sector of the device internal pull up; When unconnected WP Ready/Busy ...
Page 66
Ready/Busy# (RY/BY#) RY/BY dedicated, open drain output pin that indicates whether an Embedded Algorithm, Power-On Reset (POR), or Hardware Reset is in progress or complete. The RY/BY# status is valid after the rising edge of the final ...
Page 67
Signal Protocols The following sections describe the host system interface signal behavior and timing for the 29GL-S family flash devices. 8.1 Interface States Table 8.1 describes the required value of each interface signal for each interface state. Interface State ...
Page 68
Power Conservation Modes 8.3.1 Interface Standby Standby is the default, low power, state for the interface while the device is not selected by the host for data transfer (CE# = High). All inputs are ignored in this state and ...
Page 69
Random (Asynchronous) Read When the host system interface selects the memory device by driving CE# Low, the device interface leaves the Standby state. If WE# is High when CE# goes Low, a random read access is started. The data ...
Page 70
Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on WE# will not initiate a write cycle. 8.5.3 Logical Inhibit Write cycles are inhibited by holding OE and WE# must be Low (V 70 ...
Page 71
Electrical Specifications 9.1 Absolute Maximum Ratings Storage Temperature Plastic Packages Ambient Temperature with Power Applied Voltage with Respect to Ground All pins other than RESET# RESET# (Note 1) Output Short Circuit Current Notes: 1. Minimum ...
Page 72
Symbol V V Power Supply level below which re-initialization is required LKO and V RST and V VCS CC t Duration Note: 1. Not 100% tested. P ...
Page 73
Input Signal Overshoot V March 16, 2012 S29GL_128S_01GS_00_06 Figure 9.3 Maximum Negative Overshoot Waveform max IL V min IL – Figure 9.4 ...
Page 74
DC Characteristics Parameter Description I Input Load Current LI I Output Leakage Current Active Read Current CC1 Intra-Page Read Current CC2 CC V Active Erase/Program CC I CC3 Current (Notes ...
Page 75
Parameter Description I Input Load Current LI I Output Leakage Current Active Read Current CC1 Intra-Page Read Current CC2 CC V Active Erase/Program CC I CC3 Current (Notes Standby Current ...
Page 76
Capacitance Characteristics Parameter Symbol OUT C IN2 RY/BY# Notes: 1. Sampled, not 100% tested. 2. Test conditions T = 25° 1.0 MHz. A Parameter Symbol OUT C IN2 RY/BY# Notes: 1. ...
Page 77
Timing Specifications 10.1 Key to Switching Waveforms Waveform 10.2 AC Test Conditions Output Load Capacitance, C Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels Note: 1. Measured between V ...
Page 78
Power-On Reset (POR) and Warm Reset Normal precautions must be taken for supply decoupling to stabilize the V device in a system should have the V the package connections (this capacitor is generally on the order of 0.1 µF). ...
Page 79
Hardware (Warm) Reset During Hardware Reset (t When RESET# continues to be held at V held but not Cold Reset has not been completed by the device when RESET# is asserted ...
Page 80
AC Characteristics 10.4.1 Asynchronous Read Operations Table 10.3 Read Operation V Parameter JEDEC Std t t Read Cycle Time AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV CE t ...
Page 81
Table 10.5 Read Operation V Parameter JEDEC Std t t Read Cycle Time AVAV Address to Output Delay AVQV ACC Chip Enable to Output t t ELQV CE Delay t Page Access Time PACC t t Output ...
Page 82
Amax-A4 A3-A0 CE# OE# DQ15-DQ0 Note: Word Configuration: Toggle A0, A1, A2, and A3 Figure 10.7 Page Read Timing Diagram tACC tCE tOE ® GL-S MirrorBit Family S29GL_128S_01GS_00_06 March 16, ...
Page 83
Asynchronous Write Operations Parameter JEDEC Std t t AVAV AVWL AS t ASO t t WLAX AH t AHT t t DVWH WHDX DH t OEPH t t GHWL GHWL t t ELWL ...
Page 84
Figure 10.9 Back to Back (CE#VIL) Write Operation Timing Diagram Amax DQ15-DQ0 Amax-A0 CE# OE# WE# DQ15-DQ0 tWC tAS tAH tCS CE# tWP tDS Figure ...
Page 85
Amax-A0 CE# OE# WE# DQ15-D0 Amax-A0 CE# OE# WE# DQ15-A0 March 16, 2012 S29GL_128S_01GS_00_06 Figure 10.11 Write to Read (t ) Operation Timing Diagram CE tAH tAS tSR_W tCS tCH tOEH ...
Page 86
Figure 10.13 Read to Write (CE# Toggle) Operation Timing Diagram Amax-A0 CE# OE# WE# DQ15-A0 Parameter JEDEC Std t t WHWH1 WHWH1 t t WHWH2 WHWH2 t BUSY t SR/W t ESL t PSL t RB Notes: 1. Not 100% ...
Page 87
Addresses CE# OE# WE# Data RY/BY# Note program address program data, D Addresses CE# OE# WE# Data RY/BY# Note sector address (for sector erase valid address for reading status data. ...
Page 88
Figure 10.16 Data# Polling Timing Diagram (During Embedded Algorithms) Addresses CE OE# WE# DQ7 DQ6–DQ0 t BUSY RY/BY# Note Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array ...
Page 89
Alternate CE# Controlled Write Operations Parameter JEDEC Std t t AVAV AVWL AS t ASO t t WLAX AH t AHT t t DVWH WHDX DH t CEPH t 0EPH t t GHEK ...
Page 90
Amax-A0 CE# OE# WE# DQ15- Figure 10.20 (CE#) Write to Read Operation Timing Diagram tWC tAS tAH tOEH tWS tWH tDH tDS ® GL-S MirrorBit Family tACC tCE tDF tOE ...
Page 91
Physical Interface 11.1 56-Pin TSOP 11.1.1 Connection Diagram A23 NC for GL128S A22 A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RESET# A21 WP# RY/BY# A18 A17 RFU DNU ...
Page 92
Physical Diagram Figure 11.2 56-Pin Thin Small Outline Package (TSOP PACKAGE JEDEC MO-142 (B) EC SYMBOL MIN. A --- A1 0.05 A2 0.95 b1 0.17 b 0.17 c1 0.10 c 0.10 D 19.80 D1 18.30 ...
Page 93
FBGA 11.2.1 Connection Diagram A NC for GL128S A13 WE# 4 RY/BY Notes: 1. Ball E1, Do Not Use (DNU), a device internal signal is connected ...
Page 94
Physical Diagram – LAE064 Figure 11.4 LAE064—64-ball Fortified Ball Grid Array (FBGA PACKAGE LAE 064 JEDEC N/A 9. 9.00 mm PACKAGE SYMBOL MIN NOM A --- A1 0.40 A2 0.60 D 9.00 BSC. ...
Page 95
Physical Diagram – LAA064 PACKAGE LAA 064 JEDEC N/A 13. 11.00 mm PACKAGE SYMBOL MIN NOM A --- --- A1 0.40 --- A2 0.60 --- D 13.00 BSC. E 11.00 BSC. D1 7.00 BSC. E1 7.00 BSC. ...
Page 96
FBGA 11.3.1 Connection Diagram Supports WP# only, not WP#/ACC Notes: 1. Ball G1, Do Not Use (DNU), a device internal signal is connected to the package connector. The connector may ...
Page 97
Physical Diagram - VBU 056 0.10 C (2X) A1 CORNER 9 INDEX MARK A A1 PACKAGE VBU 056 JEDEC 9. 7.00 mm NOM PACKAGE SYMBOL MIN A --- A1 0.17 D 9.00 BSC. E 7.00 BSC. D1 ...
Page 98
... S29GL01GS11TFVyyx S29GL01GS11DHIyyx S29GL01GS11FHIyyx S29GL01GS11TFIyyx S29GL512S10DHIyyx S29GL512S10FHIyyx S29GL512S10GHIyyx S29GL512S10TFIyyx 0, 3 S29GL512S11DHVyyx (Note 2) S29GL512S11TFVyyx S29GL512S11DHIyyx S29GL512S11FHIyyx S29GL512S11TFIyyx S29GL256S90DHIyyx S29GL256S90FHIyyx S29GL256S90GHIyyx S29GL256S90TFIyyx 0, 3 S29GL256S10DHVyyx (Note 2) S29GL256S10TFVyyx S29GL256S10DHIyyx S29GL256S10FHIyyx S29GL256S10TFIyyx S29GL128S90DHIyyx S29GL128S90FHIyyx S29GL128S90GHIyyx S29GL128S90TFIyyx 0, 3 S29GL128S10DHVyyx (Note 2) S29GL128S10TFVyyx S29GL128S10DHIyyx S29GL128S10FHIyyx S29GL128S10TFIyyx S29GL_128S_01GS_00_06 March 16, 2012 ...
Page 99
... The ordering part number for the General Market device is formed by a valid combination of the following: S29GL01GS 10 Device Number/Description S29GL01GS, S29GL512S, S29GL256S, S29GL128S 3.0 Volt Core, with V Manufactured MirrorBit Eclipse Process Technology March 16, 2012 S29GL_128S_01GS_00_06 Packing Type 0 = Tray 3 = 13” ...
Page 100
Other Resources Visit www.spansion.com 14.1 Links to Software Downloads and related information on flash device support is available at http://www.spansion.com/Support/Pages/DriversSoftware.aspx Spansion low-level drivers Enhanced flash drivers Flash file system Downloads and related information on simulation modeling ...
Page 101
Specification Bulletins Contact your local sales office for details. 14.4 Contacting Spansion Obtain the latest list of company locations and contact information on our web site at http://www.spansion.com/About/Pages/Locations.aspx March 16, 2012 S29GL_128S_01GS_00_06 ...
Page 102
Revision History Section Revision 01 (February 11, 2011) Initial release Revision 02 (March 21, 2011) Global Modified document from “Advance Information” to “Preliminary” Added FBGA package offering for V1 & V2 Model Number OPN Removed KGD information, which is ...
Page 103
Section Revision 04 (October 3, 2011) Power-Up Write Inhibit Minor correction PPB Password Protection Mode Minor correction Embedded Algorithm Characteristics Updated Buffer Programming Time maximum limits table Absolute Maximum Ratings table Added clarification DC Characteristics table Output High Voltage clarification ...
Page 104
Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated ...