XC7300FM Xilinx, XC7300FM Datasheet - Page 4

• Manufacturer Part Number: XC7300FM
• Description: XC7300 CMOS EPLD Family
• Manufacturer: Xilinx

XC7300 EPLD Family
The programmable clock source is one of two global Fast-
Clock signals (FCLK0 or FCLK1) that are distributed with
short delay and minimal skew over the entire chip.
The Fast Function Block Macrocells drive chip outputs
directly through 3-state output buffers. Each output buffer
can be individually controlled by one of two dedicated
Fast Output Enable inputs or permanently enabled or dis-
abled. The Macrocell output can also be routed back as
an input to the Fast Function Block and the UIM.
Each Fast Function Block output is capable of sinking
24 mA when V
the XC7318 and XC7336 devices and all Fast Outputs
(FOs) on the XC7354, XC7372, XC73108, and XC73144
devices.
Unlike other I/Os, the Fast Function Block inputs do not
have an input register.
Product Term Assignment
Each Macrocell sum-of-product OR gates can be expanded
using the Fast Function Block product term assignment
scheme. Product-term assignment transfers product-terms
in increments of four product-terms from one Macrocell to
the neighboring Macrocell (Figure 4). Complex logic func-
tions requiring up to 36 product-terms can be implemented
using all nine Macrocells within the Fast Function Block.
When product-terms are assigned to adjacent Macrocells,
the product-term normally dedicated to the Set or Reset
function becomes the input to the Macrocell register.
.
Figure 4. Fast Function Block Product-Term Assignment
MC
MC
N
N+1
From Previous
Macrocell
4
4
CCIO
= 5 volts. These include all outputs on
Output
Polarity
Output
Polarity
Clocks
Global
Term Assignment
Term Assignment
Single-Product-
Eight-Product-
D/T
D/T
S/R
Q
Q
X5220
2-4
High-Density Function Blocks
The XC7354, XC7372, XC73108 and XC73144 devices
contain multiple, High-Density Function Blocks linked
though the UIM. Each Function Block contains nine Mac-
rocells. Each Macrocell can be configured for either regis-
tered or combinatorial logic. A detailed block diagram of
the High-Density FB is shown in Figure 5.
Each FB receives 21 signals and their complements from
the UIM and an additional three inputs from the Fast Input
(FI) pins.
Shared and Private Product Terms
Each Macrocell contains five private product terms that
can be used as the primary inputs for combinatorial func-
tions implemented in the Arithmetic Logic Unit (ALU), or
as individual Reset, Set, Output-Enable, and Clock logic
functions for the flip-flop. Each Function Block also pro-
vides an additional 12 shared product terms, which are
uncommitted product terms available for any of the nine
Macrocells within the Function Block.
Four private product terms can be ORed together with up
to four shared product terms to drive the D1 input to the
ALU. The D2 input is driven by the OR of the fifth private
product term and up to eight of the remaining shared
product terms. The shared product terms add no logic
delay, and each shared product term can be connected to
one or all nine Macrocells in the Function Block.
Arithmetic Logic Unit
The functional versatility of each Macrocell in the High-
Density Function Block is enhanced through additional
gating and control functions available in the ALU. A
detailed block diagram of the XC7300 ALU is shown in
Figure 6.
The ALU has two programmable modes; logic and arith-
metic . In logic mode, the ALU functions as a 2-input
function generator using a 4-bit look-up table that can be
programmed to generate any Boolean function of its D1
and D2 inputs as illustrated in Table 1.
The function generator can OR its inputs, widening the
OR function to a maximum of 17 inputs. It can AND
them, which means that one sum-of-products can be
used to mask the other. It can also XOR them, toggling
the flip-flop or comparing the two sums of products.
Either or both of the sum-of-product inputs to the ALU
can be inverted, and either or both can be ignored.