DSP56002RC40 Motorola Inc, DSP56002RC40 Datasheet - Page 8
DSP56002RC40
Manufacturer Part Number
DSP56002RC40
Description
24-BIT DIGITAL SIGNAL PROCESSOR
Manufacturer
Motorola Inc
Datasheet
1.DSP56002RC40.pdf
(110 pages)
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Signal/Pin Descriptions
Introduction
1-2
Note:
1. The Host Interface port signals are multiplexed with the Port B GPIO signals (PB0–PB15).
2. The SCI and SSI signals are multiplexed with the Port C GPIO signals (PC0–PC8).
3. Power and Ground lines are indicated for the 144-pin TQFP package.
D0–D23
A0–A15
CKOUT
PLOCK
GND
EXTAL
V
GND
GND
GND
GND
GND
GND
GND
PCAP
PINIT
XTAL
V
V
V
V
V
V
V
CCCK
CKP
CCQ
CCD
CCC
CCH
CCP
CCA
CCS
WR
X/Y
WT
BG
RD
DS
BR
BN
PS
BS
CK
Q
D
C
H
P
A
S
16
24
4
4
3
3
2
4
5
6
2
Figure 1-1 Signals Identified by Functional Group
Power Inputs:
PLL
Clock Output
Internal Logic
Address Bus
Data Bus
Bus Control
HI
SSI/SCI
Grounds:
PLL
Clock
Internal Logic
Address Bus
Data Bus
Bus Control
HI
SSI/SCI
PLL and
Clock
External
Address Bus
External
Data Bus
External
Bus
Control
DSP56002
DSP56002/D, Rev. 3
Communications
Event Counter
Interface (SSI)
Interface (SCI)
Synchronous
Interrupt/
(HI) Port
Interface
Control
Timer/
Mode
OnCE
Serial
Serial
Port
Port
Host
Port
2
1
2
3
8
3
MODA
MODB
MODC
RESET
H0–H7
HA0–HA2
HR/W
HEN
HREQ
HACK
RXD
TXD
SCLK
SC0–SC2
SCK
SRD
STD
TIO
DSCK
DSI
DSO
DR
MOTOROLA
Interrupt
IRQA
IRQB
NMI
Port B
PB0–PB7
PB8–PB10
PB11
PB12
PB13
PB14
Port C
PC0
PC1
PC2
PC3–PC5
PC6
PC7
PC8
Status
OS1
OS0
AA1081G
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