XCR3064XL-6CP56I Xilinx, XCR3064XL-6CP56I Datasheet - Page 9

• Manufacturer Part Number: XCR3064XL-6CP56I
• Description: XCR3064XL 64 Macrocell CPLD
• Manufacturer: Xilinx

Revision History
The following table shows the revision history for this document..
DS017 (v1.6) January 8, 2002
Product Specification
06/01/00
08/30/00
11/18/00
12/08/00
04/11/01
04/19/01
01/08/02
Date
R
Version
1.0
1.1
1.2
1.3
1.4
1.5
1.6
Initial Xilinx release.
Added 48-ball CS BGA package.
Updated to full production data sheet; corrected note in
brought High".
Added PC44 package.
Added Typical I/V curve,
Updated Typical I/V curve,
Moved I
to AC Table, renamed T
T
spec to correct a typo. Updated AC Load Circuit diagram to more closely resemble true test
conditions, added note for T
table lowering typical current draw during configuration.
FIN
spec to match software timing. Added T
CC
vs. Freq
Figure 1
www.xilinx.com
1-800-255-7778
SU
Figure
to T
Figure
POD
and
SU2
2; added
delay measurement. Updated note 5 in AC Characteristics
Table 1
2: added voltage levels.
for setup time through the OR array. Updated T
Revision
to page 1. Added single p-term setup time (T
Table
INIT
2: Total User I/O; changed V
spec. Updated T
Table 4
XCR3064XL 64 Macrocell CPLD
to read: "port enable pin is
CONFIG
spec. Updated T
OH
spec.
SUF
SU1
and
HI
)
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