CAT513 Catalyst Semiconductor, CAT513 Datasheet - Page 6

• Manufacturer Part Number: CAT513
• Description: 8-Bit Dual Digital POT
• Manufacturer: Catalyst Semiconductor

RDY/BSY
OUTPUT
PROG
DAC
DO
Doc. No. ________ 3/01 M-1
V
V
sets the DAC’s Zero to Full Scale output range where
V
full power supply range or just a fraction of it. In typical
applications V
power supply rails. When using less than the full supply
voltage V
V
READY/BUSY
When saving data to non-volatile EEPROM memory, the
Ready/Busy ouput (RDY/BSY) signals the start and
duration of the EEPROM erase/write cycle. Upon receiv-
ing a command to store data (PROG goes high) RDY/
BSY goes low and remains low until the programming
cycle is complete. During this time the CAT513 will
ignore any data appearing at DI and no data will be
output on DO.
RDY/BSY is internally ANDed with a low voltage detec-
tor circuit monitoring V
value required for EEPROM programming, RDY/BSY
will remain high following the program command indicat-
ing a failure to record the desired data in non-volatile
memory.
DATA OUTPUT
Data is output serially by the CAT513, LSB first, via the
Data Out (DO) pin following the reception of a start bit
and two address bits by the Data Input (DI).
becomes active whenever CS goes high and resumes
its high impedance Tri-State mode when CS returns low.
Tri-Stating the DO pin allows several 513s to share a
single serial data line and simplifies interfacing multiple
513s to a microprocessor.
WRITING TO MEMORY
Programming the CAT513’s EEPROM memory is ac-
Figure 1. Writing to Memory
CS
DI
REF
REF
REF
DD
/2 and V
, the voltage applied between pins V
L = Zero and V
t
o
/BUSY
/BUSY
/BUSY
/BUSY
1
REF
1
2
A0
REF
H is restricted to voltages between V
3
REF
A1
NON-VOLATILE
L to voltages between GND and V
4
DAC VALUE
CURRENT
D0
D0
H andV
5
REF
D1
D1
6
CURRENT DAC DATA
NEW DAC DATA
D2
D2
H = Full Scale. V
DD.
7
D3
D3
REF
8
If V
D4
D4
L are connected across the
9
D5
D5
DD
10
D6
D6
11
is below the minimum
D7
D7
12
DAC VALUE
VOLATILE
REF
NEW
REF
can span the
H andV
N
N+1 N+2
NON-VOLATILE
DAC VALUE
NEW
DD
REF
DD
and
DO
/2.
L,
6
complished through the control signals: Chip Select
(CS) and Program (PROG). With CS high, a start bit
followed by a two bit DAC address and eight data bits are
clocked into the DAC control register via the DI pin. Data
enters on the clock’s rising edge. The DAC output
changes to its new setting on the clock cycle following
D7, the last data bit.
Programming is achieved by bringing PROG high for a
minimum of 3 ms. PROG must be brought high some-
time after the start bit and at least 150 ns prior to the
rising edge of the clock cycle immediately following the
D7 bit. Two clock cycles after the D7 bit the DAC control
register will be ready to receive the next set of address
and data bits. The clock must be kept running through-
out the programming cycle. Internal control circuitry
takes care of ramping the programming voltage for data
transfer to the EEPROM cells. The CAT513’s EEPROM
memory cells will endure over 100,000 write cycles and
will retain data for a minimum of 100 years without being
refreshed.
READING DATA
Each time data is transferred into a DAC control register
currently held data is shifted out via the D0 pin, thus in
every data transaction a read cycle occurs.
however, that the reading process is destructive. Data
must be removed from the register in order to be read.
Figure 2 depicts a Read Only cycle in which no change
occurs in the DAC’s output. This feature allows Ps to
poll DACs for their current setting without disturbing the
output voltage but it assumes that the setting being read
is also stored in EEPROM so that it can be restored at the
end of the read cycle. In Figure 2 CS returns low before
the 13
setting is reloaded into the DAC control register. Since
Figure 2. Reading from Memory
OUTPUT
PROG
DAC
DO
CS
DI
th
clock cycle completes. In doing so the EEPROM’s
t
o
1
1
2
A0
3
A1
4
D0
5
D1
6
CURRENT DAC DATA
D2
7
D3
NON-VOLATILE
DAC VALUE
8
CURRENT
D4
9
Advance Information
D5
10
D6
11
D7
12
Note,