TC7107 TelCom, TC7107 Datasheet - Page 7

• Manufacturer Part Number: TC7107
• Description: 3-1/2 DIGIT A/D CONVERTERS
• Manufacturer: TelCom

ANALOG SECTION
cycles discussed, the circuit incorporates an auto-zero
cycle. This cycle removes buffer amplifier, integrator, and
comparator offset voltage error terms from the conversion.
A true digital zero reading results without adjusting external
potentiometers. A complete conversion consists of three
cycles: an auto-zero, signal-integrate and reference-inte-
grate cycle.
Auto-Zero Cycle
disconnected from the circuit by opening internal analog
gates. The internal nodes are shorted to analog common
(ground) to establish a zero-input condition. Additional ana-
log gates close a feedback loop around the integrator and
comparator. This loop permits comparator offset voltage
error compensation. The voltage level established on C
compensates for device offset voltages. The offset error
referred to the input is less than 10 V.
integrating resistor and capacitor values as long as they are
stable during a measurement cycle. An inherent benefit is
noise immunity. Noise spikes are integrated or averaged to
zero during the integration periods. Integrating ADCs are
immune to the large conversion errors that plague succes-
sive approximation converters in high-noise environments.
Interfering signals with frequency components at multiples
of the averaging period will be attenuated. Integrating ADCs
commonly operate with the signal integration period set to a
multiple of the 50/60 Hz power line period. (Figure 2B)
3-1/2 DIGIT A/D CONVERTERS
In addition to the basic signal integrate and deintegrate
During the auto-zero cycle the differential input signal is
The auto-zero cycle length is 1000 to 3000 counts.
Figure 2B. Normal-Mode Rejection of Dual Slope Converter
The dual slope converter accuracy is unrelated to the
30
20
10
0
TELCOM SEMICONDUCTOR, INC.
0.1/T
INPUT FREQUENCY
T = MEASUREMENT PERIOD
1/T
10/T
AZ
Signal Integrate Cycle
ential inputs connect to V
signal is integrated for a fixed time period. The signal
integration period is 1000 counts. The externally set clock
frequency is divided by four before clocking the internal
counters. The integration time period is:
common-mode range (1V of either supply) when the con-
verter and measured system share the same power supply
common (ground). If the converter and measured system do
not share the same power supply common, V
tied to analog common.
phase. The sign bit is a true polarity indication in that signals
less than 1 LSB are correctly determined. This allows
precision null detection, limited only by device noise and
auto-zero residual offsets.
Reference Integrate Cycle
V
connected across the previously charged reference capaci-
tor. Circuitry within the chip ensures that the capacitor will be
connected with the correct polarity to cause the integrator
output to return to zero. The time required for the output to
return to zero is proportional to the input signal and is
between 0 and 2000 counts. The digital reading displayed is:
DIGITAL SECTION (TC7106A)
ers necessary to directly drive a 3 -1/2 digit liquid crystal
display (LCD). An LCD backplane driver is included. The
backplane frequency is the external clock frequency divided
by 800. For three conversions/second the backplane fre-
quency is 60Hz with a 5V nominal amplitude. When a
segment driver is in phase with the backplane signal the
segment is “OFF.” An out of phase segment drive signal
causes the segment to be “ON” or visible. This AC drive
configuration results in negligible DC voltage across each
LCD segment. This insures long LCD display life. The
polarity segment driver is “ON” for negative analog inputs. If
V
IN
–
+
IN
and V
When the auto-zero loop is opened, the internal differ-
where:
f
The differential input voltage must be within the device
Polarity is determined at the end of the signal integrate
The final phase is reference integrate or de-integrate.
is internally connected to analog common and V
The TC7106A (Figure 3) contains all the segment driv-
OSC
= External Clock Frequency
–
IN
are reversed, this indicator will reverse.
T
SI
1000 x
=
f
+
IN
OSC
4
and V
V
V
REF
IN
x 1000
IN
–
. The differential input
TC7106A
TC7107A
IN
–
TC7106
TC7107
should be
3-189
IN
+
is
1
2
3
4
5
6
7
8