MAX5180 Maxim, MAX5180 Datasheet - Page 10

• Manufacturer Part Number: MAX5180
• Description: Dual / 10-Bit / 40MHz / Current/Voltage Simultaneous-Output DACs
• Manufacturer: Maxim

To disable the MAX5180/MAX5183’s internal reference,
connect REN to AV
reference may now be applied to drive the REFO pin to
set the full-scale output (Figure 3). Choose a reference
capable of supplying at least 150µA to drive the bias
circuit that generates the cascode current for the cur-
rent array. For improved accuracy and drift perfor-
mance, choose a fixed output voltage reference such
as the +1.2V, 25ppm/°C MAX6520 bandgap reference.
To enter the lower power standby mode, connect digital
inputs PD and DACEN to DGND. In standby, both the
reference and the control amplifier are active with the
current array inactive. To exit this condition, DACEN
must be pulled high with PD held at DGND. Both the
MAX5180 and MAX5183 typically require 50µs to wake
up and allow both the outputs and the reference to settle.
Dual, 10-Bit, 40MHz, Current/Voltage
Simultaneous-Output DACs
Table 1. Power-Down Mode Selection
X = Don’t care
10
Figure 4. Timing Diagram
(POWER-DOWN SELECT)
______________________________________________________________________________________
D0–D9
OUT2
OUT1
CLK
PD
0
0
1
t
DS1
DAC1
DD
. A temperature-stable, external
N - 1
t
(DAC ENABLE)
External Reference
DS2
DAC2
DACEN
0
1
X
Standby Mode
t
CP
N - 1
N - 1
N - 1
DAC1
t
DH1
POWER-DOWN MODE
N
Shutdown
Wake-Up
Standby
For lowest power consumption, the MAX5180/MAX5183
provide a power-down mode in which the reference,
control amplifier, and current array are inactive and the
DAC supply current is reduced to 1µA. To enter this
mode, connect PD to DV
connect PD to DGND and DACEN to DV
lists the power-down mode selection. About 50µs are
required for the parts to leave shutdown mode and set-
tle to their outputs’ values prior to shutdown.
Both DAC cells in the MAX5180/MAX5183 write to their
outputs simultaneously (Figure 4). The input latch of the
first DAC (DAC1) is loaded after the clock signal transi-
tions high. When the clock signal transitions low, the
input latch of the second DAC (DAC2) is loaded.
Simultaneously at the rising edge of the next clock, the
contents of both input latches are shifted to the DAC
registers and their outputs are updated.
DAC2
t
DH2
N
N
N
t
CL
DAC1
MAX5180
MAX5183
MAX5180
MAX5183
Last state prior to standby mode
N + 1
DD
OUTPUT STATE
t
CH
. To return to active mode,
Timing Information
DAC2
N + 1
N + 1
Shutdown Mode
N + 1
High-Z
High-Z
AGND
AGND
DD
. Table 1