X1286 Intersil Corporation, X1286 Datasheet - Page 18

• Manufacturer Part Number: X1286
• Description: Intersil Real Time Clock/Calendar/CPU Supervisor with EEPROM X1286
• Manufacturer: Intersil Corporation

Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte and it’s associated ACK signal. If a stop is issued
in the middle of a data byte, or before 1 full data byte +
ACK is sent, then the X1286 resets itself without per-
forming the write. The contents of the array are not
affected.
Acknowledge Polling
Disabling of the inputs during nonvolatile write cycles
can be used to take advantage of the typical 5mS write
cycle time. Once the stop condition is issued to indi-
cate the end of the master’s byte load operation, the
X1286 initiates the internal nonvolatile write cycle.
Acknowledge polling can begin immediately. To do this,
the master issues a start condition followed by the
Slave Address Byte for a write or read operation. If the
X1286 is still busy with the nonvolatile write cycle then
no ACK will be returned. When the X1286 has com-
pleted the write operation, an ACK is returned and the
host can proceed with the read or write operation.
Refer to the flow chart in Figure 12.
Read Operations
There are three basic read operations: Current
Address Read, Random Read, and Sequential Read.
Current Address Read
Internally the X1286 contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power up, the sixteen bit
address is initialized to 0h. In this way, a current
address read immediately after the power on reset can
download the entire contents of memory starting at the
first location.Upon receipt of the Slave Address Byte
with the R/W bit set to one, the X1286 issues an
Figure 11. Current Address Read Sequence
REV 1.1 7/8/04
Signals from
the Master
SDA Bus
Signals from
the Slave
www.intersil.com
S
a
t
r
t
1
Address
Slave
1
1
acknowledge, then transmits eight data bits. The mas-
ter terminates the read operation by not responding
with an acknowledge during the ninth clock and issuing
a stop condition. Refer to Figure 11 for the address,
acknowledge, and data transfer sequence.
Figure 12. Acknowledge Polling Sequence
1
1
A
C
K
Cycle complete. Continue
command sequence?
Byte load completed
Enter ACK Polling
by issuing STOP.
Continue normal
Data
(Read or Write)
nonvolatile write
Read or Write
Issue START
Address Byte
Issue Slave
PROCEED
returned?
command
sequence
ACK
YES
YES
S
o
p
t
NO
NO
Issue STOP
Issue STOP
X1286
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