DS1308 Dallas Semiconductor, DS1308 Datasheet - Page 10

• Manufacturer Part Number: DS1308
• Description: (DS1307) 64 x 8 Serial Real Time Clock
• Manufacturer: Dallas Semiconductor

AC ELECTRICAL CHARACTERISTICS
PARAMETER
SCL Clock Frequency
Bus Free Time Between a STOP and
START Condition
Hold Time (Repeated) START Condition
LOW Period of SCL Clock
HIGH Period of SCL Clock
Set-up Time for a Repeated START
Condition
Data Hold Time
Data Set-up Time
Rise Time of Both SDA and SCL Signals
Fall Time of Both SDA and SCL Signals
Set-up Time for STOP Condition
Capacitive Load for each Bus Line
I/O Capacitance
Crystal Specified Load Capacitance
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. SCL only.
11. SDA and SQW/OUT
12. The DS1308 is designed to be subjected to no more than two passes through a solder reflow process
All voltages are referenced to ground.
Logic zero voltages are specified at a sink current of 5 mA at V
loads.
I
V
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the
V
The maximum t
SCL signal.
C
I
to limit premature crystal aging effects and maintain a reasonable accuracy of ±2 minutes/month at
25 degrees C (worst case).
CCS
CCA
B
CC
IHMIN
- total capacitance of one bus line in pF.
=0V, V
specified with V
- SCL clocking at max frequency = 100 kHz.
of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
BAT
=3V.
HD:DAT
CC
has only to be met if the device does not stretch the LOW period (t
=5.0V and SDA, SCL=5.0V.
(0 C to 70 C or -40 C to +85 C; V
SYMBOL
t
t
t
t
t
HD:DAT
HD:STA
SU:DAT
SU:STA
SU:STO
t
t
f
t
C
HIGH
LOW
C
BUF
SCL
t
t
10 of 14
R
I/O
F
B
MIN
250
4.7
4.0
4.7
4.0
4.7
4.7
0
0
TYP
12.5
10
CC
=4.5V, V
MAX
1000
100
300
400
OL
CC
=GND for capacitive
UNITS
=4.5V to 5.5V)
kHz
pF
pF
pF
ns
ns
ns
s
s
s
s
s
s
s
DS1307/1308
LOW
NOTES
) of the
6, 7
5
8