74LVC138A Philips, 74LVC138A Datasheet - Page 2

• Manufacturer Part Number: 74LVC138A
• Description: 3-to-8 line decoder/demultiplexer; inverting
• Manufacturer: Philips

1. C
2. The condition is V
Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0 V; T
NOTES:
ORDERING INFORMATION
PIN CONFIGURATION
16-Pin Plastic SO
16-Pin Plastic SSOP Type II
16-Pin Plastic TSSOP Type I
1998 Apr 28
Wide supply voltage range of 1.2 to 3.6 V
In accordance with JEDEC standard no. 8-1A
Inputs accept voltages up to 5.5 V
CMOS lower power consumption
Direct interface with TTL levels
Demultiplexing capability
Multiple input enable for easy expansion
Ideal for memory chip select decoding
Active LOW mutually exclusive outputs
Output drive capability 50 W transmission lines at 85 C
3-to-8 line decoder/demultiplexer; inverting
P
f
f
i
o
PD
D
= input frequency in MHz; C
= output frequency in MHz; V
(C
= C
SYMBOL
t
is used to determine the dynamic power dissipation (P
L
PHL
C
PD
C
V
PD
/t
PACKAGES
I
CC
amb
PLH
V
2
CC
= 25 C; t
f
2
o
GND
) = sum of the outputs.
E
E
A
A
A
E
I
Y
3
2
1
0
1
2
= GND to V
7
f
i
) (C
1
2
3
4
5
6
7
8
Propagation delay
An to Yn,
E
Input capacitance
Power dissipation capacitance per
package
r
3
= t
to Yn, En to Yn
f
L
L
2.5 ns
CC
= output load capacity in pF;
CC
V
CC
= supply voltage in V;
PARAMETER
2
TEMPERATURE RANGE
SV00553
16
15
14
13
12
10
11
9
f
o
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
) where:
V
Y
Y
Y
Y
Y
Y
Y
CC
0
0
0
0
0
0
0
D
in W)
OUTSIDE NORTH AMERICA
C
V
V
Notes 1 and 2
L
CC
CC
2
= 50 pF;
= 3.3 V
= 3.3 V
DESCRIPTION
The 74LVC138A is a low-voltage, low-power, high-performance
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
The 74LVC138A accepts three binary weighted address inputs (A
A
LOW outputs (Y
The 74LVC138A features three enable inputs: two active LOW (E
and E
E
This multiple enable function allows easy parallel expansion of the
74LV138A to a 1-of-32 (5 lines to 32 lines) decoder with just four
74LV138A ICs and one inverter. The 74LV138A can be used as an
eight output demultiplexer by using one of the active LOW enable
inputs as the data input and the remaining enable inputs as strobes.
Unused enable inputs must be permanently tied to their appropriate
active HIGH or LOW state.
LOGIC DIAGRAM
74LVC138A PW
74LVC138A DB
74LVC138A D
1
1
CONDITIONS
, A
and E
2
2
) and when enabled, provides 8 mutually exclusive active
) and one active HIGH (E
2
are LOW and E
1
2
3
4
5
6
0
to Y
7
).
E
E
E
74LVC138APW DH
NORTH AMERICA
1
2
3
3
is HIGH.
74LVC138A DB
74LVC138A D
3
). Every output will be HIGH unless
A
A
A
0
1
2
TYPICAL
3.5
3.5
5.0
44
Y
Y
Y
Y
Y
Y
Y
Y
0
1
2
3
4
5
6
7
74LVC138A
SV00554
Product specification
853–1943 19308
PKG. DWG. #
15
13
12
11
10
9
7
14
SOT109-1
SOT338-1
SOT403-1
UNIT
pF
pF
ns
1
0
,